IEEE Solid-State Circuits Magazine - Fall 2017 - 75

Constant-Gm

The transconductance of an MOS
transistor such as in the CS gain
stage shown in Figure 2(a) is proportional to the transistor aspect ratio
W/L and depends on the bias current I b. The latter can be reduced to
lower the power consumption, but
the aspect ratio has to be increased
to achieve the same transconductance, therefore increasing the transistor area. This tradeoff between
the bias current and the transistor
aspect ratio can be explored by
means of the IC using the definition of the normalized source trans conductance g ms (IC ) given in [3]. The
gate transconductance G m can be
written as
Gm =

I spec4 W
·
·g (IC ),
nU T L ms

(1)

where W and L are the width and
l e n g t h o f t h e t r a n s i s t o r, n i s
the slope factor, and U T _ kT/q is
the thermodynamic voltage [3].
I spec4 _ 2nn 0 C ox U 2T is the specific
current per square, which is a fundamental parameter for a given
technology and type of transistor
(n- or p-channel), where n 0 is the
low field mobility in the channel
region and C ox the oxide capacitance
per unit area [3]. g ms is the normalized source transconductance given
by [3]

I D = I spec ·IC = I spec4 · W ·IC.
L

I D = I b = G m ·nU T ·IC ,
g ms (IC)
G m ·nU T ,
W =
L
g ms (IC) ·I spec4

(m c IC + 1) 2 + 4IC - 1
,
m c (m c IC + 1) + 2
(2)

where G spec _ I spec /U T = 2nn 0 C ox U T
and m c _ L sat /L is the VS parameter corresponding to the fraction
of the channel in which the carrier
drift velocity reaches the saturated
velocity v sat over a portion of the
channel length L sat = 2n 0 U T /v sat [3].
From the definition of IC given in
[3], the drain current in saturation
can be written as

(4a)
(4b)

Constant Gain-Bandwidth Product
An important specification that determines the transconductance of singlestage amplifiers as the CS amplifier
shown in Figure 2(b) is the GBW product GBW or unity-gain frequency
~ u given by
~u =

which can be nor ma lized to the
desi r e d t r a n s con duc t a n ce G m
according to
Ib
(5a)
= IC ,
G m ·nU T
g ms (IC)
I
spec4
1
AR _ W ·
=
. (5b)
L G m ·nU T
g ms (IC)
ib _

The normalized bias current i b
and aspect ratio AR are plotted in
Figure 3 for different values of the
VS parameter m c . It shows that the
same G m can be achieved with lower
current by shifting IC toward MI
and WI where i b saturates to unity.
This is obtained at the cost of a significant increase of the transistor
aspect ratio (or of the transistor
width W for a fixed length L ) resulting in a drastic area increase. From
this perspective, MI turns out to be
a good tradeoff between low current
and acceptable area for achieving a
given transconductance [4], [5].

G ms
G spec

= n·G m =
G spec

(3)

Solving (1) and (3) for I D and W/L
results in

G m = ~ · W ·g ,
L
CL
L ms

(6)

where C L is the load capacitance
at the drain of the transistor and
~ L _ I spec4 / (nU T C L) is a normalizing quantity corresponding actually
to the GBW of a square transistor
biased in WI. If C L is assumed to
be constant, then (6) and (3) can be
solved for I D and W/L and normalized to the desired GBW, resulting in
ib _

Ib
· 1 = IC ,
I spec4 X
g ms

AR _ W · 1 = 1 ,
L X
g ms

(7a)
(7b)

where X _ ~ u /~ L. Note that this normalization leads to the same expressions for i b and AR as in (5a) and
(5b), which are plotted in Figure  3.
Again, for achieving a given GBW
product, current can be saved by
moving the operating point toward
MI at the cost of a slight increase in

100
Normalized Bias Current ib

g ms _

From this perspective, MI turns out to
be a good tradeoff between low current
and acceptable area for achieving a given
transconductance.

100
λc = 1

10

λc = 0.3
λc = 0

10
λc = 1

1

0.1
0.01

λc = 0.3
λc = 0
0.1
1
10
Inversion Coefficient IC

1

Normalized W/L

varies with IC for a given G m, GBW,
and input-referred thermal noise
resistance R n.

0.1
100

FIGURE 3: The normalized current and W/L ratio versus IC for a constant G m and GBW.

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

75
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
