IEEE Solid-State Circuits Magazine - Fall 2017 - 76

where C w is the self-loading capacitance per unit width mostly due to overlap
and fringing field capacitances. Equations (6) and (3) can then be solved for
i b and W/L accounting for (8), resulting in the following normalized current and aspect ratio [6]-[8]:
ib _

ID · 1 =
IC
,
I spec4 X
g ms - lX

1
AR _ W · 1 =
,
L X
g ms - lX

(9a)
(9b)

Normalized Bias Current ib

100
κ=0

κ = 0.3

where l _ C w L/C L0 is the ratio of
the self-loading parasitic capacitance of a square transistor (W = L)

(10)
This is because when reducing IC
and at the same time increasing W
leads to an increase of C L and hence
a reduction of ~ u that has to be compensated by an increase of the current
to maintain ~ u constant. The curves
in Figure 4(a) are without accounting
for VS. Figure 4(b) shows i b and AR
for l = 0.3 and for different values of
m c . As expected, the impact of VS is
negligible in WI whereas the required
current to achieve the same GBW in
SI gets significantly larger with VS.
Notice that the optimum IC corresponding to the minimum current i b
when VS is present is no more given
by (10) and cannot be solved analytically, but (10) can still be used as a
first guess since IC opt is actually not
much affected by VS as shown in Figure 4(b) [7], [8].

Constant Input-Referred
Thermal Noise
The transconductance can also be
determined by the input-referred

κ=1

Ω = 0.1
λc = 0

100

10

10
κ = 0.3

κ=1

1

1
κ=0

0.1
0.01

0.1
1
10
Inversion Coefficient IC
(a)

0.1
100

100

Ω = 0.1
κ = 0.3

thermal noise resistance R n given
by [9]
Rn =

c nD
c nD
nU T
=
,
·
Gm
I spec4 ·W/L g ms

where c nD _ G m R n is the noise excess
factor, which is slightly bias dependent for a long-channel transistor
and is typically comprised between
n/2 in WI and 2n/3 in SI. For shortchannel devices c nD raises quickly
in SI due to several short-channel
effects but usually stays lower than
3 [9]. It can be approximated as [10]
(12)

c nD , 1 + a c ·IC

with a c , 0.07 [10]. Solving (11) and
(3) for I D and W/L and normalizing
to the desired R n results in
c nD ·IC
i b _ I D ·R n =
,
nU T
g ms
c nD
R n ·I spec4
AR _ W ·
=
.
L
nU T
g ms

(13a)
(13b)

The normalized bias current i b and
aspect ratio AR given by (13) are
plotted versus IC in Figure 5 for
different values of m c and a c . It
shows that the required current
for achieving a given R n in SI is significantly larger in case of a short
channel device where both m c and
a c are different than zero. Moderate
inversion is again a sweet spot for a
balanced tradeoff between current
consumption and area for achieving
a given input-referred thermal noise.

100

λc = 1
λc = 0.3

10

10
λc = 1

1

0.1
0.01

(11)

λc = 0
λc = 0.3

λc = 0
0.1
1
10
Inversion Coefficient IC
(b)

1

Normalized W/L

(8)

IC opt = 2lX (1 + lX)
+ lX (1 + lX) (1 + 2lX) 2 .

Normalized Bias Current ib

C L = C L0 + C w ·W,

to the fixed load capacitance. Equations (9a) and (9b) are plotted versus
IC for a constant GBW (X = 0.1) in
Figure 4(a) without accounting for
VS (m c = 0) [6], [8]. It shows that the
current accounting for self-loading
(l = 0.3 and l = 1) now reaches a minimum for an optimum IC given by

Normalized W/L

transistor width. Moving it further
toward WI does not gain much current and costs a lot of area [4], [5].
The assumption that the load capacitance remains constant becomes
obviously erroneous as the transistor gets wider. Indeed, since the
parasitic capacitance of the transistor is proportional to the width W,
enlarging the transistor to move the
operating point to WI makes this
parasitic capacitance contribute significantly to the load capacitance
at the drain. This can be accounted
for as illustrated in Figure 2(c) by
splitting the load capacitance into a
constant part C L0 (typically including the wire capacitance and the
capacitance of the next stage) and
a part that scales proportionally to
the transistor width W

0.1
100

FIGURE 4: The normalized current and W/L ratio versus IC for a constant GBW including self-loading capacitance: (a) without VS (m c = 0)
and (b) including VS.

76

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
