IEEE Solid-State Circuits Magazine - Fall 2017 - 80

This article illustrates the use the IC as the
main design parameter to explore the various
tradeoffs faced in the design of analog circuits.

1.0

NFmin (dB)

0.8
at 14 GHz
0.6
at 10 GHz

0.4

Measurements
Analytical Model
BSIM6

0.2
0.0
0.1

100

IC
FIGURE 13: Minimum noise figure versus IC [11], [17].

line in Figure 10 and there would be
no maximum.
Note that this FoM was successfully used by [15] to design an
ultra low-power low-noise amplifier (LNA).

Experimental Results
The three FoMs presented previously are plotted versus IC in Figure 11 and in Figure 12 for a 40- and
a 30-nm RF device from a 40- and
28-nm bulk CMOS process, respectively [12]. Despite their simplicity
and reduced number of parameters,
the analytical models fit the experimental data very well over almost
five decades of IC (current). The
small discrepancy for the last measurement point in SI is due to mobility reduction due to the vertical
field [9], which is not accounted for
in the simple model. However, this
effect is accounted for in the BSIM6
compact model [16], which perfectly
fits the measured data in Figure 11,
including at high IC.

Other FoMs
Other FoMs can be defined and expressed in terms of IC. For example,

FA L L 2 0 17

the minimum noise figure NFmin,
which gives the minimum noise
that can be achieved under proper
impedance matching conditions, also
shows a minimum at the higher end
of MI as shown in Figure 13 [11], [17].
Another example is used for the design of low-power oscillators. An
FoM including the phase noise at a
given offset frequency, the power
consumption, and the oscillation
frequency can be defined. The latter
has been evaluated for Pierce and
cross-coupled oscillators and shows
a maximum also at the edge of MI
and WI [18], [19].

Conclusions
This article illustrates the use the
IC as the main design parameter to
explore the various tradeoffs faced
in the design of analog circuits. It
can help the designer to select the
most appropriate IC setting the current and the W/L ratio. This is illustrated by looking at the simple CS
gain stage. It is shown that the same
transconductance, GBW, or inputreferred thermal noise resistance
can be achieved with lower current
by shifting the IC toward MI at the

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cost of a slight increase of the transistor aspect ratio and area.
A minimum bias current can
be found at an IC that lies in the
middle of the MI to achieve a given
GBW product when accounting for
the self-loading capacitance at the
drain. This current can be significantly less than the current required
to achieve t h e s a m e t r a n s c o n duc t a nce, GBW or input-referred
thermal noise resistance in SI, particularly under VS. Different FoMs
are then introduced, starting with
the transconductance or current
efficiency G m /I D, which tells how
much transconductance is obtained
for a given current. G m /I D is maximum in WI and decreases as 1/ IC
in SI for long channel devices and as
1/ (m c ·IC) for short-channel transistors because of VS. Another FoM key
to evaluate the RF performance of a
device is the transit frequency Ft . It
is shown that Ft follows a behavior
opposite of G m /I D, namely increasing with IC to reach the maximum
Ftpeak in SI because of VS. It is shown
that Ftpeak is simply inversely proportional to the VS parameter m c and
that does not scale as 1/L but is simply proportional to the ratio of the
oxide capacitance per unit area and
the total extrinsic gate capacitance
per unit width.
Another FoM is introduced as the
product G m /I D and Ft that helps maximizing the GBW, while minimizing
the added thermal noise at a given
bias current, which turns out to be
useful for choosing the right operating point of RF circuits such as LNAs.
It is shown that the G m /I D ·Ft FoM
reaches a maximum in MI offering
a good tradeoff between gain, noise
and current consumption.
All these FoMs can be expressed
versus IC using simple analytical
expressions that fit experimental data
very well despite requiring only four
parameters: n, I spec4, L sat, and C GeW .
All the presented FoMs are favorably
compared to measurements of shortchannel devices from 40- and 28-nm
bulk CMOS technologies and with the
BSIM6 compact model for the 40-nm

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017