IEEE Solid-State Circuits Magazine - Fall 2017 - 85

VDD
VDD

VDD
L, Q

RB2
RB2

L, Q

RB2

L, Q

LGG

C

M2
C

C
M.N.

CP

M.N.

M1
RB1

RB1

VB1

VB1

(a)

LS
Re[ZP] =

(b)

For ω >

FIGURE 3: (a) The general circuit schematic of a tuned cascode amplifier. The input matching (M.N.) is shown as a black box driving this amplifier. (b) The circuit schematic of a tuned
cascode amplifier with inductive degeneration to provide noise-free input matching.

amplifier, inductive degeneration is
commonly employed to provide a
noise-free input impedance matching [1], as shown in Figure 3(b). At low
RF frequencies, a cascode topology
has larger output resistance compared to a common-source configuration, making it possible to achieve
higher gain. In addition, the noise
contribution of the common-gate
transistor to the overall noise figure
is negligible because this transistor sees a large source-degenerated
resistance (i.e., ro1 of the commonsource device [2]).
Unfortunately, all these advantages will fade away at high frequencies toward mm-wave frequency
range where the external passives
are in the range of device parasitics.
For instance, the overall capacitance
C P at the cascode node, shown in
Figure 4, starts lowering the overall
impedance at this node at high frequencies. This means that the noise
contribution of the common-gate device to overall noise figure is no longer
assumed to be negligible. In fact, at
near-fmax frequencies (loosely defined
as frequencies around and above halffmax ), the noise figure of the cascode
topology may worsen the noise figure
by as much as 3 dB.

1
(1 - LGGCGS2ω 2)
gm 2
1

Re[ZP] < 0

√LGGCGS2

FIGURE 4: The core cascode circuit with parasitic capacitance CP, the gate-drain capacitance
CGD, and the parasitic capacitance LGG included.

VDD

RB2

ZP

P

CGD1

VDD

L, Q

RB2

M2

L, Q

C

C

M2
CBY,1

CBY,1

LC

M1

LP

M1

CBY,2

(a)

(b)

FIGURE 5: An interstage inductor to lower the noise contribution of the common-gate transistor in a cascode stage. (a) Parallel inductor LP and (b) series inductor LC.

One way to alleviate this issue is
to place a series [3] or parallel inductor [4] to partially resonate out C P
[cf. Figure 5(a) and (b)]. The parallel inductor in Figure 5(a) creates a
band-limited high impedance at the
resonance frequency, whereas the
series inductor in Figure 5(b) creates a wideband interstage filter,
extending the roll-off at the cascode
node to higher frequencies. For a CMOS
cascode stage, the drain and source

junctions of the common-source and
common-gate transistors are shared.
These shared drain and source junctions must inevitably be separated
apart if the series interstage inductor, L C , is to be used. This separation of junction regions leads to
additional parasitics at the inductor's
terminals. In addition, when considering the inductor's parasitics, the
usefulness of L C in extending the
bandwidth and lowering the noise

IEEE SOLID-STATE CIRCUITS MAGAZINE

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
