IEEE Solid-State Circuits Magazine - Fall 2017 - 86

Node 2

Node 1
V1
Cin

- +
- +
- +
CF

V1 - ∆V1 +++

Cin

-∆V +
-

- ∆V

∆V1 = ∆V

∆V

CF
CF + Cin

+
∆V
-

V1
- ∆V1 ∆V1
CX
CF

- ∆V

Cin

(a)

(b)

FIGURE 6: The conceptual circuit to demonstrate the underlying idea behind the neutralization technique.

contribution of the common-gate
transistor on the overall noise figure
becomes unclear.
Moreover, the parasitic inductance L GG of the bypass capacitor
and interconnects (Figure 4) connected to the gate of a cascode device can degrade the stability factor
of the amplifier. In fact, this inductor induces a negative resistance
at the cascode node at frequencies

below the resonance frequency of
this inductor and the equivalent
capacitance seen from the gate terminal, as also indicated in Figure 4.
Finally, at high frequencies, the
parasitic gate-drain capacitance
C GD1 of the common-source transistor in a cascode configuration establishes a feed-forward path from the
input of this common-source stage
to its output. The signal travel-

VDD

VDD
L, Q

L, Q
VS
RS

Cancellation of the
Capacitive Feedback

M.N.

C R
S

RB1

CB
VBIAS
VB1

VB1
(a)

(b)

FIGURE 7: The use of a mutually coupled inductor for neutralization of the feedback capacitor. The neutralization is realized between (a) the drain and gate and (b) the source and gate
of a common source amplifier.

VD
CGD
CGD

(1-k )L

1:1
CN

kL
VG
L = LT /2

(1-k )L

1:1

kL
L = LT /2

(a)

(b)

FIGURE 8: The circuit models for neutralized amplifiers in Figure 7(a) and (b). The circuit
model employs a T-section model followed by ideal transformer to model the center-tapped
inductor. (a) The circuit model for the amplifier in Figure 7(a), and (b) the circuit model for the
amplifier in Figure 7(b).

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

ing through this path destructively
combines with the signal amplified
by the common source, as shown in
Figure 4. The effective gain of this
stage is thus compromised. Moreover,
the real part of the output impedance
of a source-degenerated c a sco de
amplifier becomes smaller than that
of a common-source counterpart
because the intermediate node P
becomes a short at high frequencies.
This, in turn, further lowers the cascode power gain.

As described above, the cascode
topology, while providing unilateral
gain, entails several drawbacks at
high frequencies. This notion calls
for techniques that retain the original amplifier topology and surround
the amplifier with a network which
cancels the feedback capacitance.
To understand the principle of
neutralization technique, consider
the arrangement in Figure 6, where
the floating and grounded capacitors
C F and C in exemplify the feedback
capacitance and the amplifier's input
capacitance, respectively. A negative
voltage drop at node 2 will induce a
negative voltage drop at node 1 due
to the presence of C F . To keep node 1
quiet, an opposite charge needs to be
created to cancel the delta-charge on
the upper and left plates of capacitors
C in and C F , respectively. This can be
accomplished by sampling the deltavoltage across C F and producing its
inverse with the aid of an inverting
voltage-controlled voltage source and
apply this delta-voltage to a capacitor
C X [see Figure 6(b)]. Assuming equal

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017