IEEE Solid-State Circuits Magazine - Fall 2017 - 87

capacitances, C P = C X , the voltage at
node 1 will then remain quiet.
We use the aforementioned general principle to develop neutralizing networks around the main
amplifier. Noting that the transistor
is essentially a multiterminal component, this neutralizing network
can be placed between the output
terminal (typically drain or collector) and any of the remaining two
terminals to cancel the feedback
parasitic capacitance. Shown in Figure 7 are two examples in which the
neutralization is realized by forming
a passive feedback between drain
and gate [5], as in (a), or between the
drain and source [6], as in (b).
In both examples, the neutralizing capacitor is realized using the
gate-drain overlap region of an MOS
device to ensure that its structure
resembles that of the gate-drain
overlap capacitance of the main
common-source transistor. Therefore, they exhibit the same behavior
in the presence of process and temperature variations. Also, in both
circuits, a center-tapped inductor is
employed to generate voltage phasors of opposite signs at its up and
bottom terminals. Assuming an ideal
magnetic coupling (i.e., k = 1) and
equal loading on both sides of the
center-tapped inductor, the neutralizing capacitance should be equal to
the parasitic gate-drain capacitance.
However, in practice, the coupling
coefficient, k, is less than unity. k
will get closer to unity at very high
frequencies where a center-tapped
one- or half-turn folded microstrip
line can produce the required inductance. Figure 8(a) and (b) shows the
equivalent circuits, replacing mutually coupled inductors in the circuits of Figure 7(a) and (b) with a
T-section equiv a lent model [7 ].
With equal loadings, if the T-section
model is excited from its two sides
by a differential voltage, the circuit
will remain balanced for C N = C GD .
As mentioned earlier, neutralization occurs completely if the terminal voltages of the center-tapped
inductor r em a in dif fer ential. In

VD

CGD
(1-k )L (1-k )L
1:1

CGD

CN
CN

YL k L

VG

(1-k )L (1-k )L

1:1

kL

VG

L = LT /2

YL

L = LT /2

(a)

(b)

FIGURE 9: The circuit models for neutralized amplifiers with load admittance YL in Figure 7
(a) and (b). (a) The circuit model for the amplifier in Figure 7(a), and (b) the circuit model for
the amplifier in Figure 7(b).

CN

CN
VS

VS
-

+

+

-

VDD

L, Q

L, Q

M.N.

-

M.N.
C

CN

CN
VS

VS
+

+

C

M.N.

M.N.

-

ISS

FIGURE 10: Neutralization in differential amplifiers. A pair of cross-connected capacitors will
neutralize the feedback parasitic capacitance.

practice, however, the two sides
of the center-tapped inductor a r e
loaded by the unequal impedances.
Figure 9(a) and (b) replicates Figure 8(a)
and (b), while including the load admittance YL . Ideally, the voltage changes
DV1 and DV2 should have the same
magnitude and opposite phase. Nevertheless, YL creates phase mismatch

between these two quantities. Using
the equivalent circuit in Figure 8(a)
and (b), straightforward I-V equations
reveals that DV1 - DV2 is calculated
to be
DV1 - DV2 = - ~ 2 LC N (1 - k)
N
# V e j (+NV - +DV )
DV

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
