IEEE Solid-State Circuits Magazine - Fall 2017 - 88

VDD = 1.8 V
L

1 : 1.95 CL CBY
RL = 50 Ω

CBY LGG 0.89 : 1
RB1

RS = 50 Ω

LS

Ls = 100 pH
L = 320 pH
LGG = 450 pH
(W/L)1 = 28.8 µm/180 nm
(W/L)2 = 28.8 µm/180 nm
CL = 19.4 fF

Ideal
Transformer

RB1 = 1 MΩ
All Q's = 12

Ideal VB1 = 0.9 V
Transformer
(a)
VDD = 1.8 V
LT
VS

CBY LGG 1.3 : 1
RS = 50 Ω

1 : 1.2 CL CBY
RL = 50 Ω

RB1

LS

Ideal
VB1
Transformer

Ideal
Transformer

Ls = 100 pH
LT = 640 pH
LGG = 810 pH
(W/L)1 = 28.8 µm/180 nm
CL = 46.5 fF
RB1 = 1 MΩ
All Q's = 12

(b)

FIGURE 11: (a) The circuit schematic of a cascode amplifier with inductive degeneration designed and simulated in a CMOS 180-nm process.
(b) The circuit schematic of a CGD -neutralized common-source amplifier. Both amplifiers have been designed to operate at a 28-GHz center
frequency. All component values have been included.

and see the equation at the bottom
of the page where G eq and B eq are
the conductance and susceptance
of t he equiv a lent a d m i t t a n c e
Yeq (= YL + j~C GD f o r F i g u r e 9 (a ),
= YL + j~C N for Figure 9(b), respectively. Equation (5) verifies that,
for two important special cases,
the gain and phase offset between
DV1 and DV2 is zero, namely, 1)
for any arbitrary load admittance,
YL, and when the two sides of the

center-tapped inductor are perfectly
coupled (k = 1) or 2) for partially
coupled inductors (k 1 1) and when
there is no mismatch between the
loadings of two sides.
For the circuit of Figure 7(a),
the neutralizing network is placed
between the input and output terminals. The inductor would also be
part of the output tank circuit. On
the other hand, the center-tapped
inductor in Fig ure 7(b) is placed

~L ^k + 1h G eq
- tan -1
2 - ~L ^k + 1h^~C N + B eqh
~L 61 - ~ 2 LC N ^1 - k 2h@ G eq
#
2
1 - ~ LC N - ~L 61 - ~ 2 LC N ^1 - k 2h@ B eq

\N V - \D V = tan -1

R
V1/2
^2 - ~L ^k + 1 h^~C N + B eqhh2 + (~L (k + 1) G eq) 2
S
W
NV
=S
2
W
2
DV
~
~
LC
L
1
N
2
Se
o + ^~L 61 - ~ 2 LC N ^1 - k 2h@^G eqh ) W
S 61 - ~ 2 LC N ^1 - k 2h@ B eq
W
SS
WW
T
X

88

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

between the input and the common terminal, forcing them to be
in opposite phase. This means that
ideally the transconductance will
be boosted by 6 dB [6]. However,
this g m-boosting is mainly used to
compensate for the resistive source
degeneration associated with the
loss of the center-tapped inductor.
One additional drawback regarding the neutralized amplifier in Figure 7(b) is that the presence of large
bypass capacitance contributes to
significant phase error between the
two terminals of the inductor. This
makes the design of a perfect neutralizing network extremely challenging as this phase error needs to
be accounted for during the design
of the center tapped inductor.
On the other hand, neutralization
in differential amplifiers can be done
with no explicit use of inductors. In
fact, the output terminals of opposite
polarity readily exist in a differential
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
