IEEE Solid-State Circuits Magazine - Fall 2017 - 94

Table 1. For ECG signal acquisition from
the chest, 60-dB CMRR might be sufficient while EEG signal measurement
from the head needs more than 100-dB
CMRR because the EEG signal is much
weaker than the ECG and uses a much
smaller electrode. For the same reason, low noise with high input impedance readout circuits are required for
EEG application.

EEG

CMRR

60 dB

110 dB

Noise

5 nVrms

0.5 nVrms

Input
impendance

10 MX

100 MX

dc headroom

±300 mV

±50 mV

AMP

ADC

< x10

> 16 bit
HighRes. ADC

SNR

At
Electrode

AMP

ADC

> x100

10-14 bit

High-Gain
Amplified

LowRes. ADC
SNR

Amplitude

Low-Gain
Amplified

Amplitude

At
Electrode

HPF

ECG

Electrode

PARAMETERS

Electrode

TABLE 1. THE MINIMUM
REQUIREMENTS FOR ECG AND EEG.

ADC
Noise

Signal Chain

FIGURE 4: Readout system approaches.

R1
RG

-
+

R1
-
V2

VOUT

VREF

Parameters

First Stage

Second Stage

Differential Gain

1+2R1/RG

R3/R2

Common-Mode Gain

σR × R3/R2

(a)

Noise RTI
C + C2 + Cp
a 1
C1

2
× VOTA V1

C1
Cp

CMRR
1
σC21 + σC22 + σC2p

VOUT

+
C2

VREF

R
(b)
FIGURE 5: A popular IA architecture: (a) classical 3-op-amp IA and (b) capacitive IA.

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

Instrumentation Amplifier
For the biopotential acquisition system, the first circuitry to interface
with the electrode is an instrumentation amplifier (IA). Then the amplified and conditioned signal is applied
to an analog-to-digital converter (ADC)
for further-stage digital signal processing. Figure 4 compares two approaches to constitute the combination
of an IA and an ADC. The first approach
(a) employs a dc-coupled low-gain IA
followed by a high-resolution ADC.
Owing to a large dc offset from the
electrode, the maximum gain of the
IA is usually limited not to make the
IA saturated to the supply voltage. For
a high signal-to-noise ratio (SNR), the
low-gain IA is compensated by the
high resolution of the ADC to resolve
the small analog signal in a fine scale.
On the other hand, another approach
[Figure 4(b)] filters out a large dc offset signal with a high-pass filter (HPF)
at inputs. Then the gain of the dc-free
IA need not be limited and is able to
be high, enabling the system to adopt
a low- resolution ADC for the same
SNR as the dc-coupled system [Figure 4(a)]. As you can easily figure out,
the approach in (a) is much simpler at
the cost of higher power consumption
as it needs low-noise delta-sigma ADC
with wide bandwidth but low-noise
IA. It preserves challenge at the electrode handing it over to the ADC. On
the contrary, the system in [Figure
4(b)] eliminates dc challenges at the
IA stage, allowing for a high-gain IA
followed by a successive approximation register ADC, which makes it
much more power efficient. Nonetheless, since the HPF requires a
very high time constant, it is rather
area consuming and slow to respond
to the abrupt potential change at
the electrodes.

Classical 3-Op-Amp
Instrumentation Amplifier
Figure 5(a) represents a dc-coupled
classical three-op-amp IA that has
been widely adopted in commercial
products. It consists of two-stage
amplifiers with resistive feedback.
The first stage has balanced and high

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017