IEEE Solid-State Circuits Magazine - Fall 2017 - 95

Figure 6(a) shows another class of IA
topology [6] using resistors for defining
the gain to refine the 3-Op-amp IA. It is
referred to as current-balanced IA (CBIA)
since it works in the current domain.
It comprises a transconductance (TC)
stage with input buffer and R1 and a
transimpedance (TI) stage with output

TABLE 2. A COMPARISON OF CLASSICAL 3-OP-AMP IA AND CAPACITIVE IA.
SPEC

3-OP-AMP IA

CAPACITIVE IA

Gain

(1+2R/RG)

C1/C2

CMRR

1/vR

Noise RTI

V2R

Input impedance

1/j~Cp

1/j~C1

Power

3 × Pop-amp

POTA

dc headroom

VDD/gain

VDD

Input CM range

< VDD

VDD

1/vC

+V2Thermal

V2Flicker

Transconductance (TC)
CP

×1

Transimpedance (TI)

IIN

VIN-
CP

×1

×1
R2

VIN+

b × (V2Thermal + V2Flicker)

VO+

Gain = R2/R1
VO-

×1

IIN

Gain
(AV)

CMRR

Input
Impedance

Noise RTI
(Thermal + 1/f)

R2/R1

1/σBUF

1/CP

2 × VBUF +VR1 +VR2/AV

Dynamic
Range

IIN × R1

(a)
IIN + IDC+
VIN+

×1
IIN

VIN-

IIN

×1
IIN + IDC-
fCHOP

×1

VO+

×1

VO-

To circumvent the dc offset issue,
Figure 5(b) introduces an ac-coupled
capacitive IA (popular for implant
applications where low power consumption is the primary concern [5]). It
is composed of an operational transconductance amplifier (OTA) with capacitive feedback, defining the gain
of IA (C2/C1). The great merit of this
IA is that C1 completely blocks any dc
voltage (electrode polarization voltage) at inputs, achieving maximum
rail-to-rail dc headroom. The feedback
resistor, R, plays a role in biasing the
high impedance input nodes and
determining high-pass corner frequency with C2. A single OTA, which
drives only high-impedance capacitive nodes, means that it can be
designed with extremely low power
consumption. C1 needs to be high
enough to mitigate the noise elevation
by parasitic capacitance Cp, considering the required input impedance.
The CMRR is capacitor mismatch
dependent. Table 2 summarizes and
compares the performance of two
popular IA architectures. While the
3-Op-amp IA has high input impedance, the capacitive IA has advantages
in dc headroom, low power consumption, and rail-to-rail input commonmode range.

buffer and R2. The input differential
voltage is converted into current IIN at
the TC stage, and the output voltage is
generated at the TI stage with the current flow through R2. Therefore, the
differential gain is R2/R1, whereas the
common-mode gain is defined by the
mismatch of the gain at the input buffers,
making CMRR buffer-mismatch dependent rather than resistor-mismatch

Capacitive IA

Current-Balanced
Instrumentation Amplifier

input impedance with a differential gain of (1+2R1/RG) and common
mode gain of one. Meanwhile, the
second-stage amplifier is a differential to single-ended converter with
a differential gain of (R3/R2). Notice
that the common-mode gain is proportional to the resistor mismatch.
The CMRR is then mismatch dependent, and the matching between R2
and R3 is of significant importance.
Increasing the gain of the first stage
not only helps to improve CMRR but
also has an effect to reduce the total
noise of the circuit as the noise of the
second stage is scaled by the first
stage gain when it refers to the input.
It is worth noting that increasing the
first-stage gain is not as easy as the
dc-coupled input contains large dc
offset voltage.

IDC+
fCHOP

IDC-

VDC, Electrode = IDC × R1

dc
Extraction

dc Servo Loop (DSL) Cancels Out
dc Offset Current Flowing Through R1
(b)
FIGURE 6: Current-balanced IA: (a) CBIA topology and (b) CBIA with chopping and dc servo.

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017