IEEE Solid-State Circuits Magazine - Spring 2014 - 19

Self-Calibrating Data Converters
Although the charge-redistribution
ADCs revolutionized MOS data converters, the accuracy was limited to
10 bits or lower. Through the 1970s,
high-precision ( ≥12 bits), high-speed
(≥1 kS/s) data converters were predominantly built in 'hybrid' technologies in which multiple components
are packaged in a relatively large
enclosure. The core component that
determined the accuracy was an R-2R
ladder DAC where the metal thin-film,
typically NiCr, resistors were factory
laser-trimmed to the desired accuracy
against a golden standard -accurately
calibrated input voltages. Obviously,
such data converters were expensive
due to the individual laser trimming,
and bulky due to hybrid packaging.
As an example, Analog Devices introduced a family of then state-of-the-art
DAS11xx series ADCs in 1982. The DAS
1140 was a 16b 30 kS/s ADC without a
SHA, and the DAS1153 a 15b 30 kS/s
ADC with a SHA [3]. The DAS1140
had dimensions of 51 mm x 51 mm x
11.2 mm, and a volume price of $149,
which in today's dollars is $360. At
the end of 1970s, dynamic component matching technique surfaced,
which enabled high accuracy without
laser trimming [4]. However, due to a
large supply voltage requirement for
stacked current dividers, this technique was not generally compatible
with MOS technologies.
The challenge that Prof. David
Hodges put on my doctoral research
in June of 1981 when I joined his
group was to come up with a viable
MOS alternative to such beasts. This
would then enable cohabitation of
high performance digital and analog
circuits on a single die. The initial
goal was 16-bit accuracy, which was a
very tall order at the time. Although
the ingenious capacitor array chargeredistribution ADC had opened an era
of MOS data converters [2], the accuracy, mainly determined by capacitor
matching, had been limited to 10 bits.
Bahram Fotouhi and Prof. Hodges had
developed a MOS 12-bit ADC by a
clever combination of resistor-ladder
main-DAC and a charge-redistribution

Figure 1: The MOS charge-redistribution ADC [2]. It samples the input directly on the
weighted capacitor array eliminating a SHA and nonlinearity due to parasitic capacitance.
10 bit accuracy was achieved.

sub-DAC [5]. While 12-bit monotonicity was achieved, the accuracy
(integral linearity or INL) was actually limited to 6 bits due to the poor
matching characteristic of the diffused resistors in the main DAC.
Therefore, the difficulty was how to
achieve high accuracy given 6 bits

(resistors) and 10 bits (capacitors) of
matching accuracy. Laser trimming
was a non-starter because the primary
driver for MOS technologies is the
high level of integration and low cost.
Furthermore, standard MOS technologies were incompatible with laser
trimming, anyway.

Figure 2: The 15 and 16 bit hybrid ADC's from Analog Devices, Inc, introduced in 1982.
They were 102mm x 102mm x 11.2mm and 51mm x 51mm x 11.2m in size [3].

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2014