IEEE Solid-State Circuits Magazine - Spring 2014 - 21

The self-calibrating ADC improved its own
accuracy without a factory calibration or
a golden standard for the first time.
produced after about 6 moths of hard
labor in the laboratory. Although fully
functional, the accuracy was disappointing 12-bits. Hundreds of different tests were performed in an
attempt to improve the accuracy with
no avail. Some sort of a hysteresis-like
behavior was observed in the comparator, which I attributed to traps due to
contamination at s
-ilicon-silicon dioxide interface. Another fabrication run
with a special care in clean gate oxide
growth resulted in no improvement.
Yet another fabrication run, this time
in the brand new lab, new equipment,
and new process flows to improve
the interface quality did nothing to
improve the accuracy at initial test.
However, there was one important
distinction in this batch - slowing the
clock frequency significantly improved
the accuracy even though the previous batches showed no improvement.
Although designed for 50 kS/s rate,
when run at 12 kS/s, it achieved 15-bit
accuracy, which was deemed the best
achievable given that the capacitor array matching was 1 bit short of
expectation [7]. The h
-ysteresis-like
behavior in the comparator led to later
research at MIT on oxide traps and
electron and hole tunneling that theoretically and experimentally explained
the observed behavior [8]. The reason
why the accuracy of the last batch
improved at lower speed, I believe,
was because it had different trap density versus depth profile. Apparently,
the lower density of deeper traps in
the new batch allowed relaxation of
hysteresis at slower clock frequencies.

Epilog and Conclusion
Until well after I thought of the self-calibration idea, I believed I was the first
one to have recognized the property
of the binary weighted capacitor array
and exploited it to measure capacitor
mismatch - nothing remotely similar

had turned up in any of the circuit-type
journal or conference publications. I discovered later, to my dismay, McCreary
had thought of the same principle and
had applied it to characterize capacitor
mismatch characteristics [9]. This had
been published in IEEE Transactions on
Instrumentation and Measurements in
1979 - a journal I had not thought was
relevant to data converters. Of course,
McCreary used the principle for capacitor matching characterization, not for
calibrating ADC's, but he recognized
the important symmetry in a binary
weighted capacitor array and used it
to measure capacitor mismatch. Along
with his pioneering work in chargeredistribution ADC's, his work laid the
foundation for the self-calibrating ADC
work presented here.
The self-calibrating ADC improved
its own accuracy without a factory
calibration or a golden standard for
the first time. Many other calibration
methods followed for various different types of ADC's including successive-approximation, pipeline, and
delta-sigma ADC's, ultimately finding
applications in other analog circuits
in the form of now popular digitallyassisted analog circuits.

References

[1] I. Young, D. Hodges, and P. Gray, "Analog
NMOS sampled-data recursive filter," in
1977 IEEE Int. Solid-State Circuits Conf. Dig.
Technical Papers, Feb. 1977, pp. 156-157.
[2] J. L. McCreary and P. R. Gray, "All-MOS charge
redistribution analog-to-digital conversion
techniques. I," IEEE J. Solid-State Circuits,
vol. 10, no. 6, pp. 371-379, Dec. 1975.
[3] Analog Dialog, Analog Devices, MA, Nov.
1982, vol. 16.
[4] R. J. Van de Plassche and D. Goedhart,
"A monolithic 14-bit D/A converter,"
IEEE J. Solid-State Circuits, vol. 14, no. 3,
pp. 552-556, June 1979.
[5] B. Fotouhi and D. Hodges, "High-resolution A/D conversion in MOS/LSI,"
IEEE J. Solid-State Circuits, vol. 14, no. 6,
pp. 920-926, Dec. 1979.
[6] Z. Boyacigiller, B. Weir, and P. Bradshaw,
"An error-correcting 14b/20ms CMOS A/D
converter," in 1981 IEEE Int. Solid-State
Circuits Conf. Dig. Technical Papers, Feb.
1981, vol. XXIV, pp. 62-63.

[7] H.-S. Lee, D. A. Hodges, and P. R. Gray,
"A self-calibrating 15 bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 19,
no. 6, pp. 813-819, Dec. 1984.
[8] T. L. Tewksbury, H.-S. Lee, and G. A.
Miller, "The effects of oxide traps on the
large-signal transient response of analog
MOS circuits," IEEE J. Solid-State Circuits,
vol. 24, no. 2, pp. 542-544, Apr. 1989.
[9] J. L. McCreary and D. A. Sealer, "Precision
capacitor ratio measurement technique
for integrated circuit capacitor arrays,"
IEEE Trans. Instrum. Meas., vol. 28, no. 1,
pp. 11-17, Mar. 1979.

About the Author
Hae-Seung Lee received the B.S. and
the M.S. degrees in Electronic Engineering from Seoul National University,
Seoul, Korea, in 1978 and 1980 respectively. He received the Ph.D. degree in
electrical engineering from the University of California, Berkeley, in 1984,
where he developed self-calibration
techniques for A/D converters.
Since 1984, he has been on the
faculty in the Department of Electrical Engineering and Computer
Science, Massachusetts Institute of
Technology, Cambridge, MA, where
he is now Professor and the Director of Center for Integrated Circuits
and Systems. He has acted as Consultant to Maxim Integrated, Analog
Devices, Inc., Wilmington, MA, and
MIT Lincoln Laboratories. He has
served the Technology Advisory
Committee for Samsung Electronics,
Cypress Semiconductor, and Sensata
Technologies. He also co-founded
SMaL Camera Technololgies, Inc., and
Cambridge Analog Technologies, Inc.
His research interests are in the
areas of analog integrated circuits with
the emphasis on analog-to-digital converters in scaled CMOS technologies.
Prof. Lee is a recipient of the 1988 Presidential Young Investigators' Award,
and a co-recipient ISSCC Jack Kilby
Outstanding Student Paper Award in
2002 and 2006. He has served a number of technical program committees
for various IEEE conferences, including the International Electron Devices
Meeting, the International Solid-State
Circuits Conference, the Custom Integrated Circuits Conference, and the
IEEE Symposium on VLSI circuits. He is
an elected AdCom member and Treasurer of the Solid-State Circuits Society. Prof. Lee is a Fellow of IEEE.

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