IEEE Solid-State Circuits Magazine - Spring 2014 - 26

Figure 1: M. Bujatti, D. McDaniel, and D. Hodges in the Integrated Circuits Lab (1963).

Figure 2: Prof. Oldham at an early -epitaxial deposition system (1963).

Figure 3: Bipolar-JFET counting bistable circuit. D. Hodges, Prof. Pederson (1963).

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IEEE SOLID-STATE CIRCUITS MAGAZINE

of ERL, said last week. He predicted
that 'substantially more than the current 10 per cent of ERL's total effort
will be devoted to this area,' when
the new semi-conductor integrated
circuits fabrication laboratory and
electron beam microscopy facility
begin operating."
And indeed, that is what happened. The plans became reality in
1962 with the construction of the
Integrated Circuits Laboratory in Cory
Hall. An 1,800 square-foot laboratory
space was extensively renovated at
a cost of about $30,000, creating a
vacuum systems and test area, furnace and epitaxial room with hydrogen plumbing, a chemistry room,
dark room, and a microscope room.
Equipment to enable processing of
complete bipolar circuits was added,
which brought the total cost up to
just under $100,000. The first working integrated circuit on a 3/4-inchdiameter wafer, emerged at the end
of 1962. The brochure, Research Program in Electrical Engineering, for the
school year of 1963/64 proudly lists:
"A special laboratory is equipped
for diffusion and evaporation processes,
metallographic
studies,
photo-resist etching and electroplating" and features "Graduate students
David Hodges and Marina Bujatti in
the solid-state laboratory conferring
with technician Dorothy McDaniel
on microscopic appearance of integrated circuit and operating vacuum
system for thin film fabrication." (See
Fig. 1 and 2.)
The following professors had
research projects and graduate students in the early Integrated Circuits
Lab: A. C. English, T. E. Everhart, W. G.
Oldham, R. S. Muller, D. O. Pederson,
R. S. Pepper, S. Wang, and R. M. White.
S. R. Pedersen, research specialist
was in charge of the lab, D. McDaniel and G. Becker provided technical
support [1]. The Integrated Circuits
Laboratory Manual compiled in 1966
lists processes for wafer preparation
(¾ inch diameter), epitaxial growth,
photolithography, furnace operations, vacuum evaporation, in-line
testing, assembly, and typical process

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2014

IEEE Solid-State Circuits Magazine - Spring 2014 - Cover1
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