IEEE Solid-State Circuits Magazine - Spring 2014 - 37

Data
SP−HV

8
ID (mA)

ID (mA)

15

5

10

Data
SP−HV

10
5

6
4

5

10
15
VDS (V)

20

0

25

3
2
1

2

0
0

Data
SP−HV

4
ID (mA)

20

0

5

(a)

10
15
VDS (V)

20

25

0

0

5

10
15
VDS (V)

(b)

20

25

(c)

Figure 2:  The measured and modeled I D for a 65-V LDMOS transistor in a 0.13-μm power BiCMOS technology; VGS = 2-8 V in 1-V steps.
(a) W = 60 nm, (b) W = 12 nm, and (c) W = 3 nm .

isolation (STI) device [1], and an RF
device [2], respectively. In the figures, L denotes the length of the
intrinsic MOS transistor region of
each device. High-voltage devices are
also made with a structure similar
to that of Figure 5 but with the substrate and drain drift region being a
blanket n -type epi and the p -body
being a p region that stretches from
the body/source regions to under
the gate. For very high-voltage applications (up to 700 V), LDMOS transistors have longer drift regions than
for, say, 80-V operation and may
include field plates akin to the flap
shown for the RF device in Figure 7.
LDMOS transistors in advanced BCD
technologies may be built on siliconon-insulator substrates (replace the

buried layer in Figure 6) and may use
deep trench, rather than junction,
isolation (not shown). A significant
gate width W , which is the dimension perpendicular to the cross sections of Figures 5-7, is often needed
and is achieved by using multiple
device fingers connected in parallel. To avoid high fields that lower
the breakdown voltage, the ends
of adjacent fingers may be merged
using circularly annular gate and
drain extensions, leading to racetrack-shaped layouts with an even
number of gate fingers. The figures
show n-channel devices but p-channel equivalents are often available as
well in BCD technologies.
There are some significant differences between these structures and

conventional low-voltage MOS transistors. First, they are clearly asymmetric with respect to source and
drain and have extended, lightly
doped drain (or drift) regions
between the drain edge of the intrinsic MOS transistor region and the
edge of the heavily doped n + drain
contact region. L dr denotes the length
of this region, which may be composed of more than one physically
different subregion. Second, the body
may be formed from an outdiffusion and, therefore, is nonuniformly
doped along the channel (and is often
shorted to the body). Third, the gate
can overlap part of the drift region
(sometimes with two separate oxide
thickness regions; see Figure 5).
Finally, there are other differences

1
4

0.6

CGB (fF)

CGG /CGG, max

0.8

0.4

Data
SP−HV

0.2
0

−5

−2.5

L

0
VGS (V)

2

0

2.5

Data
SP−HV

5
-2
-10

-5

0

5

10

15

VGS (V)

Figure 3:  The measured and modeled C GG for 45-V extended drift
region LDMOS transistors in a 0.25- nm power BiCMOS technology;
VDS = 0 V, L = 120 (lowest curve), 1.26, and 0.63 nm.

	

Figure 4:  The TCAD and modeled C GB; VDS = 0, 4, 12 V.

	 IEEE SOLID-STATE CIRCUITS MAGAZINE	

s p r i n g 2 0 14	

37
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2014
