IEEE Solid-State Circuits Magazine - Spring 2014 - 44
LDMOS transistors are also widely
used for high-power wireless
infrastructure applications.
conditions [28]. The integration of
small-signal conductances, as well
as capacitances, from measured s
-parameters converted to y -parameters, has also been used to characterize the nonlinear intrinsic current and
charge components of Figure 15 [29],
[30]. To avoid extrapolation errors for
measurement-based table models,
numerical data fitting using artificial
neural networks has been used [30].
More physically based RF LDMOS
models have been developed. The
Motorola electro-thermal model [31]
includes standard MOS transistor
modeling concepts such as threshold voltage and gain factor and has
simple DIBL and CLM models, but
the main bias dependence is empirical, an `a -power law"-type model
[32] for the gate bias dependence
and a hyperbolic tangent dependence on drain bias. The tanh function provides a smooth saturating
characteristic and is often used in
the RF community for FET modeling.
In [33], a surface potential-based
model for the intrinsic MOS transistor is combined with a physical
description of the drift region that
includes velocity saturation and partial lateral depletion.
Open and Other Issues
Advanced LDMOS models such as
SP-HV address most of the issues
listed in the "LDMOS Modeling Needs
and Approaches" section, but some
are still open research issues or are
better handled outside of the core
LDMOS model.
The modeling of NLD would
increase accuracy for LDMOS transistors with out-diffused body regions
but, in practice, is difficult. The
decrease in channel doping from
source to drain has two significant
affects on the behavior of the intrinsic MOS portion of the device. First,
44
s p r i n g 2 0 14
as the device is turning on, the drain
end of the channel is more strongly
inverted than the source end, so the
effective channel length appears to
be small at low VGS and to increase
as VGS increases above the threshold. This gives a peaked shape to
g m (VGS) . Second, at VDS = 0 the stronger level of inversion at the drain cf.
the source means that C SG ! C DG .
In fact C SG 1 C DG, and the amount
of asymmetry depends on VGS . As
VGS increases near the threshold the
drain end inverts first, so the intrinsic C DG is large and increases with
increasing VGS, as more of the channel
inverts, but C SG remains small. Once
the source end of the channel starts
inverting, the intrinsic gate capacitance splits between the source and
drain (the source contact is no longer
isolated from the channel by a weakly
inverted and therefore low conductance region), hence C SG increases
rapidly and C DG decreases rapidly
with increasing VGS . C DG is therefore
nonmonotonic with increasing VGS,
increasing as the drain end becomes
inverted and then decreasing when the
source end inverts. The drift region
resistance of SP-HV gives a peaked
shape to g m (VGS) (see Figure 11), and
C dr,inv in Figure 9 gives an asymmetry
between C SG and C DG (see Figure 13).
These behaviors are qualitatively correct but do not quantitatively capture the asymmetry of the intrinsic
MOS region because the model of that
region used in SP-HV is symmetric.
The simplest approach to NLD
modeling, at the cost of computational expense, is to use a series connection of sections for the intrinsic
MOS channel region, each with different doping levels. This has been done
for a surface potential-based model
[34]-[35] and also with BSIM3 [36], but
the costs are a significant increase
in model complexity and simulation
IEEE SOLID-STATE CIRCUITS MAGAZINE
time and potential convergence
issues when the transistor is turned
off and the nodes between sections
become high impedance. In the inversion charge-based approach, NLD has
been incorporated into small-signal
modeling [37] and dc current modeling [38]. As yet, there is no nonsectional large signal model for NLD; the
development of one would be a big
step forward, especially for the surface potential approach.
An additional open research item
is that it is not possible to accurately
model capacitances for devices with
laterally nonuniform channel doping via terminal charges [40]. The
only known way to properly reproduce measured behavior is via a
sectional model.
LDMOS devices are often large
with on-resistances of the order
of a few milliohms, and therefore
they can be significantly affected
by parasitic series resistance from
the source and drain interconnect
metal. The current flow in the source
and drain metal is often perpendicular to the current flow through
the transistor, which leads to a twodimensional distributed resistive
system. Closed-form solutions for
such systems have been reported
[39], but these are bias dependent
and specific to a particular layout
or layout style. Often many layout
variations are used, and it is not
practical to handle all of these in a
compact model. A better approach is
to embed parasitic metal resistance
calculations in the process design
kit (PDK) and have the computed
values be netlisted by the PDK or to
split a device into multiple fingers
or cells and let the simulator handle
the interconnect network. The latter
can also model problems from the
nonuniform turn-on or turn-off of a
device, but it increases the simulation time because of the multiplicity
of model instances used.
The SOA and breakdown are also
of practical interest and importance and can have quite complex
dependencies on layout. The inclusion of breakdown in a model is
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