IEEE Solid-State Circuits Magazine - Spring 2015 - 12

A C ircu it for All Season s

Behzad Razavi

The StrongARM Latch

T

The StrongARM latch topology finds
wide usage as a sense amplifier,
a comparator, or simply a robust
latch with high sensitivity. The term
"StrongARM" commemorates the use
of this circuit in Digital Equipment
Corporation's StrongARM microprocessor [1], but the basic structure was
originally introduced by Toshiba's
Kobayashi et al. [2]. The StrongARM
latch has become popular for three
reasons: 1) it consumes zero static
power, 2) it directly produces rail-torail outputs, and 3) its input-referred
offset arises from primarily one differential pair. In this column, we
study the circuit and its properties.

was later modified as depicted in
Figure 1(b) [3]. We first study the
latter and then point out the differences among these versions.
The latch of Figure 1(b) consists
of a clocked differential pair, M 1-M 2,
two cross-coupled pairs, M 3-M 4 and
M 5-M 6, and four precharge switches,
S 1-S 4 . The circuit provides rail-torail outputs at X and Y in response
to the polarity of Vin1 - Vin2 . We
describe the operation in four phases.
In the first phase, CK is low; M 1
and M 2 are off; nodes P, Q, X, and Y
are precharged to VDD; and the circuit
reduces to that shown in Figure 2(a).
In the second phase, CK goes
high, S 1-S 4 turn off, and M 1 and
M 2 turn on, drawing a differential
current in proportion to Vin1 - Vin2 .
With M 3-M 6 initially off, this current
flows from C P and C Q [Figure 2(b)],
thereby allowing VP - VQ to grow
and possibly exceed Vin1 - Vin2 .
That is, this phase can provide

Basic Operation
Figure 1(a) shows the original StrongARM latch, reported in [2] without
M 8 and in [1] with M 8 . The circuit
Digital Object Identifier 10.1109/MSSC.2015.2418155
Date of publication: 25 June 2015

voltage gain. We call this phase
the amplification mode. Since
the tail current is fairly constant
during this period, we can write
VP - VQ . (g m1, 2 Vin1 - Vin2 /C P, Q ) t,
where g m1, 2 denotes the small-signal transconductance of M 1 and M 2,
and C P, Q = C P = C Q .
As VP and VQ fall to VDD - VTH N ,
the cross-coupled NMOS transistors
turn on (third phase), allowing part
of the drain currents of M 1 and M 2 to
flow from X and Y [Figure 2(c)]. The
amplification mode therefore lasts
for approximately (C P, Q /I CM) VTHN
seconds, where I CM is the commonmode (CM) current drawn from each
capacitance. The voltage gain in this
mode is roughly given by [4]
Av .

g m1, 2 VTHN
.
I CM

The behavior of the latch in the
third phase can be analyzed with the
aid of the equivalent circuit shown

VDD
CK

M5

M3

VDD
CK

M5
S1

Vout

X

VDD

Q
M1

M8

M2

Vin2

M7

CK
(a)

Figure 1: (a) The original and (b) modified StrongARM latch topologies.

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s p r i n g 2 0 15

S4
Vout

X

M4

IEEE SOLID-STATE CIRCUITS MAGAZINE

CK

M6

S3

Y

P
Vin1

CK

M6

Y

M3

M4

P

Q

Vin1

M1
CK

(1)

M2
M7
(b)

Vin2

S2
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015
