IEEE Solid-State Circuits Magazine - Spring 2015 - 14
VDD
VDD
M6
M5
M6
X
Vin1
Y
M2
M1
Vin1
Vin1
M2
CK
M7
CK
M7
(a)
(b)
Figure 3: (a) Latch without ac cross-coupled NMOS pair and (b) the resulting static current.
RS Latch
X
StrongARM
Latch
Y
Figure 4: The StrongARM latch followed
by the RS latch.
Interestingly, the degeneration caused
by C P and C Q raises x reg by a factor
of 1 - C X, Y /C P, Q . Since, in practice,
C X, Y includes the input capacitance
of the stage following the comparator
and is hence greater than C P, Q , the
cross-coupled NMOS transistors provide little regeneration in this phase.
The output voltages VX and VY continue to fall until they reach VDD - VTHP ,
at which point M 5 and M 6 turn on [Figure 1(e)] and the circuit enters the fourth
phase. The positive feedback around
these transistors eventually brings one
output back to VDD while allowing the
other to fall to zero.
X
M3
Y
M4
P
Q
M1 M2
Vin1
CK
Vin2
M7
Figure 5: Offset cancellation by programmable capacitors.
14
s p r i n g 2 0 15
It is important to appreciate the role
of each transistor in the StrongARM
latch of Figure 1(b). Besides M 1-M 2
and M 7, the remaining devices also
serve critical purposes.
■ Transistors M 3-M 4 cut off the dc
path between VDD and ground at
the end of the fourth phase, avoiding static power drain. To understand this point, let us omit M 3
and M 4 as shown in Figure 3(a)
and assume a differential input,
Vin1 - Vin2, of about 100 mV around
a common-mode (CM) level near
VDD /2. When the latch is clocked,
VX falls, VY rises, and M 5 turns off.
Consequently, the circuit reduces to
that in Figure 3(b), drawing a static
current from VDD . (This does not
occur for rail-to-rail inputs.)
■ Transistors M 5 and M 6 principally
restore the output high level to VDD;
without them, the CM discharge
at X or Y would yield a degraded
high level (if Vin1 - Vin2 is small).
■ Switches S 1 and S 2 play two roles:
a) remove the previous states
at nodes P and Q, suppressing
dynamic offsets, and b) establish
an initial voltage of VDD at these
nodes, allowing amplification before
M 1 and M 2 enter the triode region.
Both of these points distinguish the
topology of Figure 1(b) from that in
Figure 1(a). The original StrongARM latch fails to equalize VP and
VQ accurately because M 8 turns
off near the end of the precharge
mode. Without M 8, the dynamic
offset would prove even more
IEEE SOLID-STATE CIRCUITS MAGAZINE
serious. Moreover, the circuit has
little voltage gain in the amplification mode for VP and VQ begin at
VDD - VTHN . Since in this case M 3
and M 4 turn on before significant
gain accrues, they contribute a
greater offset.
■ Switches S 3 and S 4 precharge X
and Y to VDD, ensuring that M 5
and M 6 remain off during the initial amplification and negligibly
raise the offset.
The StrongARM latch generates
invalid outputs ^VX = VY = VDDh for
about half of the clock cycle. For the
subsequent logic to interpret the
outputs correctly, an RS latch must
follow the circuit. Figure 4 shows a
typical arrangement where inverters serve as buffers between the
two latches and allow the RS latch to
toggle only if VX or VY falls.
The power consumed by the StrongARM latch of Figure 1(b) arises from primarily the charge and discharge of the
capacitances. It is therefore roughly
equal to fCK (2C P, Q + C X, Y ) V 2DD, where
fCK is the clock frequency and the factor of 2 accounts for the discharge
of both P and Q to near ground in
every cycle.
Offset
If operating as a sense amplifier or a
comparator, the StrongARM latch must
achieve a sufficiently small inputreferred offset voltage. As explained
in the previous section, the precharge
action of S 1-S 4 in Figure 1(b) keeps
M 3-M 6 off initially, thereby reducing
their offset contribution. In a typical
design, the mismatches between M 3
and M 4 are divided by about a factor
of A v . 4 when referred to the input,
and those between M 5 and M 6 by
about a factor of ten (because these
transistors turn on only near the end).
Thus, M 1 and M 2 become the dominant contributors.
Since the amplification mode
provides voltage gain by the flow of
charge from C P and C Q , one can create asymmetry by making C P ! C Q
and hence cancel the circuit's offset. Illustrated in Figure 5 [5], [4],
the idea is to establish different
discharge rates at P and Q. Writing
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