IEEE Solid-State Circuits Magazine - Spring 2015 - 24

Demod

IF1 =

RF
N+1

LO1 =

 N 
 N + 1  RF



PLL

DIVN

Figure 14: Sliding-IF receiver architecture.

signals, which are usually generated by running the frequency synthesizer at a higher frequency and
then dividing down to get signals
with a 90° phase shift. This requires
a divide ratio of at least two and ideally four, which means the phaselocked loop (PLL) has to run at four
times the RF frequency, with a corresponding high power penalty.
A receiver architecture suited
for low power implementation is
the "sliding IF" architecture, which
inherits benefits from both the
superheterodyne and direct conversion approaches. As shown in
Figure 14, this is a dual conversion
architecture, so again the image
rejection is relaxed by selecting
a suitably high first IF. The second mix brings the wanted signal
down to a low or zero IF for channel
selection and demodulation. This
architecture differs from direct conversion or superheterodyne in the
generation of the LO signals. The
second LO is generated by an integer
divide of the first LO, so there is no
need for independent PLLs-essentially the second LO comes "for free."

Furthermore the second frequency
conversion is usually complex, but
choosing the divide ratio N to be a
multiple of two (or preferably four)
allows the I and Q LO signals to be
easily generated. For a given divide
ratio N, the first LO will be N/ ^N + 1h
times the RF frequency, or just

Achieving a very low average power for a
wireless system typically make extensive
use of duty cycling.
below the wanted frequency-this
is in contrast to direct conversion,
where the PLL may have to generate
two or four times the wanted RF in
order to get good quadrature. The
second LO is then 1/ (N + 1) times
the RF, which thus shifts the wanted
signal down to 0 Hz. As the wanted
RF frequency varies, so does the IF,
hence the name "sliding IF" since the
position of the wanted signal at the
first mixer output "slides around" as
the RF channel varies. As a result of

Input
ASK/OOK
Input Signal
Quench
Oscillator

Superregenerative
Oscillator (SRO)

Quench

Output

Figure 15: Super-regenerative receiver architecture.

s p r I n g 2 0 15

these benefits, the sliding IF architecture has recently become popular
as an optimal receiver architecture
for very low power wireless receiver
implementation [5]-[9].
A receiver architecture that has
recently emerged for ultra-low-power
implementation is the super-regenerative receiver illustrated in Figure 15
(in practice this architecture was proposed in the early 1920s around the
same time as the superheterodyne
receiver, but the superheterodyne
became dominant because of its superior selectivity and flexibility). At
the heart of the super-regenerative
receiver is an oscillator which is
tuned to oscillate at the RF input frequency, and which is coupled to the
RF signal received at the antenna.
This "super-regenerative oscillator"
(SRO) is also controlled by a second

IEEE SOLID-STATE CIRCUITS MAGAZINE

"1"

"0"

lower frequency quench oscillator
which as its name suggests, periodically quenches or damps the
SRO signal causing the oscillations
to stop.
When the quench oscillator releases the SRO, the high frequency
SRO oscillations begin to build up.
If there is no RF input signal present, then the SRO has to start oscillating entirely on its own and the
amplitude of oscillations will build
up slowly and will not have reached
a significant level before the quench
signal damps the process again.
However, if the SRO is released and
an input RF signal at the SRO frequency is present, the RF signal will
couple into the SRO and force oscillations to build up very quickly before the quench signal damps them
again. This architecture therefore
detects the presence or absence of
an input RF signal, so is used for detection of an amplitude shift keyed

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015