IEEE Solid-State Circuits Magazine - Spring 2015 - 30

Original Device

Scaled Device
Wiring

Voltage, V

V/α
Gate
n+ Source

w
tox

n+ Drain

Results:
Density Increases by α 2
Speed Increases by α

tox/α
n+

Power/Circuit Decreases by α 2
W/α
n+

Wire RC Unchanged by Scaling

L /α

Doping α ⋅ NA

p Substrate, Doping NA

Figure 1: Scaling principles for MOS technology.

Electric Field Increased by ε
Generalized
Scaling Factor

Physical Parameter
Layout Dimensions,
L, W, etc.
Gate Insulator, tox

1/α
1/α
ε/α

Voltage, V
Doping
Concentrations

εα

Circuit Speed (Goal)
Circuit Power
Power Delay Product
Power Density

α
ε 2/α 2
ε 2/α 3
ε2

Figure 2: Generalized scaling approach.

This article will start with a review
of the original scaling principles and
will show how they were generalized to account for increasing electric field and used successfully for
many generations of CMOS scaling.
I will then present my view of an
approach to scaling which I developed in the early years of this century when the power supply voltage
was scaled into the range of 1 V and
transistor off current became a limit
to further scaling of the threshold
voltage, V T. Finally I will discuss the
present challenges and what I see
as the best path to improve energy
efficiency as we progress toward
what I hope will be the ultimate lowvoltage CMOS technology.

s p r I n g 2 0 15

Review and Update of
Generalized Scaling
Figure 1 illustrates the original scaling principles that I presented at
the 1972 IEDM. The small team I led
discovered that simply reducing all
MOS transistor dimensions, while
reducing voltage and increasing
doping concentration by the same
amount, produces a smaller transistor with the same electric field pattern as the original transistor. When
the wires are also scaled down by
the same amount, the integrated-circuit density, speed, and power consumption all are improved as shown
in the figure. In this "constant electric field" scaling scenario, the most
remarkable benefit is the increased
energy efficiency, often expressed
in MIPS/watt, improves by the cube
of the scaling factor a 3 due to the
increased speed and reduced power
per circuit.
After some early success of scaling, people were resistant to scaling the power supaply below 5 V, so
Giorgio Baccarani worked with my
small group at IBM to generalize the
scaling principles. In the drawing of
the scaled device, it is seen that the
depletion regions can be kept the
same size if the applied voltage is
scaled less and the substrate doping is increased more. This concept
of generalized scaling is illustrated
in Figure 2. It has been broadened

IEEE SOLID-STATE CIRCUITS MAGAZINE

from the original by introducing an
electric field parameter, f, which
represents the increase in electric
field as voltage is reduced more
gradually than the device dimensions. Even if the electric field factor f increases, for some time it has
been thought that a reasonable goal
is to increase the circuit speed by the
channel-length scaling factor, a. This
assumes any tendency to increase
the average carrier velocity because
of the higher lateral field is offset by
mobility reduction from the higher
vertical field and increased effects
of parasitic resistance and capacitance. These generalized scaling
rules show that the active power for
a given circuit scales as f 2 a 2 while
the power density scales as f 2 .
Figure 3 shows a plot of electric
field E, defined as VDD/L, as a function of channel length for high-performance MOS technology was
prepared from my personal knowledge and archives, with VDD indicated at some milestone values of L.
It shows how the electric field has
increased rapidly through the history of scaling down channel length.
Part of the increased field is clearly
associated with the transition to
CMOS and the desire to maintain a
5-V power supply as long as possible. The trend line over many generations of scaled CMOS shows that E
is proportional to 1 L . Therefore,

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015