IEEE Solid-State Circuits Magazine - Spring 2015 - 31

Optimized Scaling with an
Off-Current Limit
The generalized scaling relationships
assumed in the past that the device
leakage was not significant. However, at the 90-nm generation
with gate lengths in the order of
50-70 nm, the point was reached
for high-performance CMOS with a
supply voltage in the order of 1.2 V
where the transistor "off current" for
worst-case threshold voltages can be
a significant part of the total power.
This represents a point where the
threshold voltage VT has reached an
optimum value for this particular
supply voltage. For the next generation, scaling the voltage lower and
the VT lower does not give the lowest total power for the given performance. In fact, if the power supply
voltage is reduced, the optimum VT
is actually somewhat higher.
Figure 4 gives a modeled result of
energy per operation versus performance for a 90-nm ASIC technology,
where the VT has been optimized at
each supply voltage for a projected
logic switching activity (10% of the
clock frequency) based on 20 stages
of fan-out of four inverters between
latches. A measured result for early
65-nm high-performance logic technology is shown for comparison,
where the axes are normalized as

50
Electric Field, VDD /L (V/µm)

E ∝ 1/√L
1V

CMOS
1.5 V

2.5 V

nMOS
5V
12 V

1
0.01

0.1

L (µm)
Figure 3: Evolution of voltage scaling, VDD, with length.

shown. In this measurement, VT
increases as the supply voltage is
reduced due to reduced DIBL and
fortuitously maintains optimum balance between ac and dc energy consumption. Because the optimization
is fairly flat over a broad range of dc/
ac energy, measurements like this are
not sensitive to the details. It should
be noted that the applied voltage in
the model and the measurement is
directly across the circuit and does
not account for voltage drop in the
power distribution system, so the
actual power supply voltage may be

considerably higher than the numbers indicated in the figure. Curve fitting shows that energy per operation
varies with VDD2.5 in this experiment.
This is because the switching energy,
often expressed as CV2, is affected by
the nonlinearity of the capacitance.
The intrinsic charge transferred in a
switching event is related to the overdrive voltage, the applied voltage
minus an "effective threshold voltage," which decreases substantially
as the applied voltage is reduced.
The normalized relationship in
Figure 4 between energy/operation

2.5
Energy/Computation (fJ/µm)

V was actually scaled proportional to
L . I believe this trend arose to
maintain
smooth
performance
growth with scaling by reducing V
and VT gradually, while avoiding the
rapid growth in standby power if VT
were scaled more rapidly. It can be
shown using the generalized scaling
relationships that the energy efficiency, MIPS/watt, improved as a 2
(i.e., 1/L2) in that time period. However, the increase in electric field
parameter, f, over that part of the
CMOS era is a factor of five, which
means the power density must have
increased by a factor of 25. This
explains very well the power crisis in
CMOS which we know happened in
the early 2000s and caused the leveling off of clock speeds.

90 nm ASIC (Lg = 60 nm), Model
65 nm HP (Lg = 35 nm), Data

2.0

1.06 V

1.0 V

1.5
0.8 V

1.0
0.6 V

T = 100°C
Activity = 10%

0.5
0.62 V
0.0

100

150

200

fCLOCK × LG (m/s)
* Vt Optimized at Each Voltage to Minimize Energy
* Energy Per Computation Proportional to VDD 2.5
Figure 4: Optimum leakage-constrained voltage scaling.

IEEE SOLID-STATE CIRCUITS MAGAZINE

s p r I n g 2 0 15

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015