IEEE Solid-State Circuits Magazine - Spring 2015 - 51

Near-Threshold
The idea of sacrificing performance
for improved power or area is not
new; instead, it is fundamental to
circuit design. An early work argued
[A. Chandrakasan et al., JSSC, 1992]
that architectural parallelism, through
pipelining and replicating function
blocks such as ALUs allows for reasonable performance while leveraging voltage scaling to minimize power
(though not necessarily minimum
energy). By using an analytical model
of power and performance tradeoffs,
architectural parallelism was shown
to be more effective than technological techniques, such as transistor sizing, for achieving good speed after
voltage scaling.
Recent microprocessor architecture papers [B. Zhai et al., ISLPED,
2007; R.G. Dreslinski et al., Proc.
IEEE, 2010] have advocated for parallelizing a workload across many
low-voltage, energy-efficient cores,
distributing the task to balance
the slow clock frequency from low

voltage operation. Despite using
more cores to run the task than at
nominal voltage, energy savings can
be achieved because dynamic energy
has a quadratic dependence on voltage, E dynamic \ Vdd 2, yet the number
of cores needed is initially linear
with Vdd. This can be seen from the
task runtime's dependence on supply voltage, Ttask \ Vdd/ ^Vdd - Vt h2,
and simplifies to Ttask \ 1/Vdd if
supply voltage is much higher than
threshold voltage. Therefore, if a
task can be parallelized across cores
with little overhead, only a linear
number of cores must be added
to match task completion time,
whereas quadratic energy savings
are achieved. Of course, at supply
voltages close to threshold these
assumptions break down.
Even for performance insensitive
applications, achievable energy gains
are limited by static energy (from
leakage currents), which becomes
dominant at very low voltages. Since
task completion time increases
exponentially close to threshold, if
performance is constrained then the
number of cores needed for parallelization rapidly increases at low voltage. In [Pinckney et al., DAC, 2012]
we provided a systemic definition of

1.8

Voltage (V)

1.4
1.2
1
0.8

Vopt (w/Overheads)

0.6
0.4
0.2
0
180 nm

10x

Vnom
Median Energy Gain at Vopt

1.6

near-threshold to better understand
how close to threshold is practical
for many workloads and then using
this definition to examine trends
across technology nodes. In this
methodology, energy is minimized
subject to a performance constraint;
specifically, that latency is fixed to
that of a single core running a workload at high voltage.
As core voltage is reduced and its
clock frequency decreases, a workload is parallelized across cores until
the target latency is achieved. This
iso-latency analysis is workloaddependent, and parallelization overheads, arising from algorithmic and
architectural sources, are assessed
through system-level simulations of
the SPLASH-2 benchmark suite [S.C.
Woo et al., ISCA, 1995]. Additionally,
circuit energy and performance scaling are simulated with SPICE models of six industrial processes from
180 nm to 32 nm. A key finding is
that, across the scientific benchmarks
studied, the near-threshold region
tracked roughly 200-400 mV above
Vt , as shown in Figure 2. Across the
SPLASH-2 benchmarks in 32 nm, parallelism across 12 cores is needed on
average. Additionally, NT energy gain
was decreasing from 8× in 180 nm to

Median Cores at Vopt (Nopt)

applications. Unlike ULV designs, NTC
is intended for general-purpose computing applications that have moderate performance requirements and do
not parallelize perfectly.

Vt
130 nm

90 nm
65 nm
Technology

45 nm

32 nm

0x
180 nm 130 nm

90 nm 65 nm
Technology

45 nm

0
32 nm

Figure 2: Left, minimum energy points, blue lines, when considering algorithmic and architectural parallelism overheads for SPLASH-2
benchmarks across six technology nodes. This near-threshold region tracks approximately 200 mV-400 mV above threshold voltage, purple
line. Nominal voltage is shown with the black line. Right, median energy gain from running at near-threshold instead of nominal, and number
of cores parallelized across SPLASH-2 benchmarks. Near-threshold had ~8× energy gain in 180 nm and has reduced to 4× in 32 nm.

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015