IEEE Solid-State Circuits Magazine - Spring 2015 - 56

Near-threshold holds promise for improving the
energy efficiency of modern processors as process
scaling continues to slow.

early low-power designs focused
on pushing minimum voltage as
low as possible, while ensuring no
functional errors [A. Wang, ISSCC,
2004]. Recent interest has shifted to
wide-range voltage scaling designs,
which strive to maintain good performance and energy across a wide
voltage range, from near-threshold
to super-threshold.
An academic example of a manycore, 3D-stacked processor and
DRAM concept is the Centip3De
project from the University of Michigan [D. Fick et al., ISSCC, 2012]. The
90-nm system is arranged in clusters of four cores, where one to four
cores can be active depending if
the workload demands are for single-threaded performance or high
energy efficiency. In single-core
mode, the ARM Cortex-M3 processors run at 1.15 V and 80 MHz with
an efficiency of 860 DMIPS/W. In
four-core mode, the processors run
at 0.65 V and 10 MHz with a peak
efficiency of 3930 DMIPS/W, over
4.5 times as efficient compared to
single core mode. The L1 caches run

0.9

Energy/Cycle (nJ)

0.8

at integer multiples of the core frequencies to time-multiplex requests
reducing collisions in cache access.
A wide-range voltage scaling
Pentium-class, IA-32 core from Intel
demonstrates respectable performance from 280 mV to 1.2 V [S. Jain
et al., ISSCC, 2012]. Characterization
of the standard cell libraries was
done at both high and low voltages
to optimize and identify wide-range
scaling performance. Standard cells
with poor delay scaling in the presence of variation were pruned from
the library. The minimum energy for
the 32-nm test chip was observed
at 450 mV for the core supply,
reducing energy consumption by
4.7× over nominal 1.2-V operation,
shown in Figure 7. The memory is
on a separate power domain than
logic, so as to not violate the 0.55-V
memory retention voltage. Synthesis targets were very important as
well, with the low-voltage targeted
design achieving approximately 67%
clock frequency than a high-voltage
targeted design scaled down. The
design also features programmable

32 nm CMOS, 25° C

0.7
0.6
4.7 X

0.5

Total Energy
Leakage Energy
Dynamic Energy

0.3
0.2
0.1
0.0
0.3
0.55

0.4
0.55

0.5
0.55

0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
Logic Vcc/Memory Vcc (V)

1
1

1.1
1.1

1.2
1.2

Figure 7: A wide-range Intel IA-32 processor exhibits minimizes energy at 450 mV, 4.7×
less than nominal 1.2-V operation. Below 450 mV, leakage dominates total energy.

s p r i n g 2 0 15

Conclusions
Near-threshold holds promise for
improving the energy efficiency of
modern processors as process scaling continues to slow. Increased
transistor packing densities will
enable advanced voltage scaling
techniques. Initial near-threshold
designs have shown promise, yet
many obstacles remain before NTC
can be widely adopted. Variability
remains one of the biggest challenges for low-voltage operation but
variation tolerant techniques, such
as soft clocking and in-situ monitoring, can help mitigate these issues.
Improved topologies for blocks
that traditionally scale very poorly
because of sensitivity to mismatch,
such as SRAMs, demonstrate that
low-voltage operation is possible.

References

0.4

0.2
0.55

delay buffers to tune for skew
between processor blocks.
Near-threshold many-core architectures will require efficient interconnect fabrics that scale well to
different voltages. Intel proposed
a wide-range, 340 mV-to-0.9 V, FinFET network-on-chip demonstrated
in 22 nm FinFET [G. Chen et al.,
ISSCC, 2014]. The chip is partitioned
into a 16 × 16 mesh with 256 separate power and clock domains. The
energy efficiency of the network,
highest bandwidth per watt, was
achieved at 400 mV and 18.3 Tb/s/W
as compared to 7.0 Tb/s/W at 0.9-V
nominal supply. Specialized widerange
near-threshold
processor
blocks, such as the SIMD permutation engine, have also been explored
by Intel [S. Hsu et al., ISSCC, 2012].

IEEE SOLID-STATE CIRCUITS MAGAZINE

1) Background + Near-Threshold Computing
[1] R. Dennard et al., "Design of ionimplanted MOSFET's with very small
physical dimensions," IEEE J. Solid-State
Circuits, 1974.
[2] A. Chandrakasan et al., "Low-power CMOS
digital design," IEEE J. Solid-State Circuits,
1992.
[3] R. G. Dreslinski et al., "Near-threshold
computing: reclaiming Moore's law
through energy efficient integrated circuits," Proc. IEEE, Feb. 2010.
[4] H. Esmaeilzadeh et al., "Dark silicon and
the end of multicore scaling," in Proc.
ISCA, 2011.

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015