IEEE Solid-State Circuits Magazine - Spring 2015 - 67

really radio frequency design via
S-parameters.
Batting cleanup was Barrie Gilbert
with his tale of Dr. B.J. Tee's amazing
translinear circus, featuring artful
arrangements of BJTs. The award for
the best line goes to Gilbert, whose
answer to the question "What is your
favorite circuit?" was simply "I love
all my children equally."

-Richard Schreier
Panel Coorganizer

Following Prof. Kawahito's revelations, Prof. Rinaldo Castello demonstrated how simply connecting one end of a compensation capacitor to a different node can have dramatic impact on the stability of a rail-to-rail amplifier under heavy load. (Legal disclaimer: IEEE neither recommends nor
endorses Rinaldo's practice of writing equations on the windshield of his car on the way to work.)

Moore's Law Challenges Below 10 nm: Technology,
Design, and Economic Implications

M

Moderated by Dimitri Antoniadis
(Massachusetts Institute of Technology, Cambridge, United States) and organized by Bing Sheu (TSMC, Hsinchu,
Taiwan), Kathy Wilcox (AMD, Boxborough, Massachusetts, United States),
and Ali Keshavarzi (Cypress, San Jose,
California, United States), the ISSCC
Monday evening panel "Moore's Law
Challenges Below 10 nm: Technology, Design, and Economic Implications" included six panelists who explored major scenarios for the future
of Moore's law: 1) extending silicon,
2) going beyond silicon, and 3) going
beyond complementary metal-oxidesemiconductors (CMOS):
* Mark Bohr, Intel, Hillsboro, Oregon, United States
* Jack Sun, TSMC, Hsinchu, Taiwan
* Liam Madden, Xilinx, San Jose,
California, United States
* Mark Hill, University of Wisconsin, Madison, Wisconsin, United
States
* Geoffrey Yeap, Qualcomm, San
Diego, California, United States

Dr. Jack Sun (vice president/CTO at TSMC) remarking on IC chip scaling following Moore's
law: from a few transistors in the early 1960s to hundreds of transistors on a chip in the late
1960s, then to about 7 billion transistors in 2010 for the 28-nm node with key technological
innovations, such as copper and low-K materials to form the back-end, SiGe-stress to enhance carrier mobility, immersion technique to extend the life of optical lithography, high-K/
metal-gate transistors to reduce gate leakage-and so on.

■
■

■

Digital Object Identifier 10.1109/MSSC.2015.2418472
Date of publication: 25 June 2015

* Jo De Boeck, IMEC, Heverlee, Belgium.
The panelists focused on
new scaling rules for logic and memory
the impact of future scaling trends on
semiconductor technology and design
how the industry will continue to
attract the investment dollars necessary to support the pace of scaling
we have been accustomed to and

attract young talent to the semiconductor industry
■ how to continue to scale power
efficiently
■ how to manage cost and economic
considerations going forward.
Further scaling will require the
use of double photo-exposure double
etching (2P2E), FinFET 3-D transistor,

IEEE SOLID-STATE CIRCUITS MAGAZINE

s p r i n g 2 0 15

67



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015

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