IEEE Solid-State Circuits Magazine - Spring 2015 - 68

Liam Madden (corporate vice president at Xilinx) explaining 3D stacking, such as vertically
stacking N dies that can reduce average wiring length by 1/SQRT(N) and average RC by 1/N.
Stacking also handles dies from different technologies such as the digital FPGA die in 28-nm
technology and analog A/D converter and D/A converter dies in 65-nm technology, which
can be stacked together. The net result is increasing connectivity between dies by one order
of magnitude with a similar improvement in pJ/bit.

Dr. Mark Bohr (Intel senior fellow) summarizing future challenges and how to deal with them.

Prof. Mark Hill (University of Wisconsin) addressed the salient difference between 21st-century computer architecture versus its 20th century counterpart. Twentieth-century computer
architecture supports single-chip in a standalone computer, with performance via invisible
instruction-level parallelism. The components are from predictable technologies, such as
CMOS, SRAM, and disks. By comparison, key features of 21st-century computer architecture
include spanning sensors to clouds, emphasizing performance, and security, privacy, availability, and programmability, among others.

and even extreme-ultraviolet or multiple electron-beam to enable millions of cores on a chip at 2-nm node
by around 2020, as predicted.
By comparison, an average human
brain consists of about 100 billion neural
cells that correspond to 1 T transistors,

s p r i n g 2 0 15

with very high energy efficiency at about
20-W power dissipation.
Continual innovation in devices
and materials are needed to meet
performance, power, and area scaling requirements. Next, III-V channels, nanowires, tunneling FET, and

IEEE SOLID-STATE CIRCUITS MAGAZINE

spintronics are a few items on the
radar screen.
In terms of packaging, heterogeneous system integration using system-on-chip (SOC), 2.5D, or 3D is to
be considered. Continual lowering of
the cost per transistor will also be a
key driving force.
In lithography, extreme-ultraviolet lithography will be helpful, but
the key question is, when? On production development, design effort
and mask cost are to be considered
together and could lead to a refocus
on general purpose designs.
Dr. Geoffrey Yeap (Qualcomm
vice-president) examined Moore's
law challenges in the design sector,
where market- and application-specifics are important factors:
■ die cost, which is determined by die
size, wafer cost, and manufacturing
yield as well as by time to volumeproduction and time to high-yield
■ an emphasis not only on 1D scaling in CPU logic density but also
system scaling and integration of
SoCs for end user value.
The current technological pace
is too busy chasing 1D scaling (e.g.,
from four years/node to two years/
node, and now ~1.5 year/node). Not
all technology nodes are created equal:
e.g., the 0.13 um, 65 nm, and 28 are all
sweet technology nodes.
Dr. Jo De Boeck (IMEC CTO) speculated beyond CMOS, including novel
materials, device, and computing
paradigms in four distinct areas:
■ charge diffusion transport, where the
MX2-FET device is a good candidate
■ tunneling transport, where, the 3D
tunneling FET, bilayer graphene tunneling FET, and MX2 tunneling FET
are good candidates
■ wave computing spin logic, which
includes plasmonics, spin wave
devices, and the spin torque majority gate as good candidates.
■ motto/piezo mechanical switch;
in motto/piezo mechanical switch
area, devices fabricated by nanoelectromechanical system technology are good candidates.
-Bing Sheu
Compiled by Katherine Olstein

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2015