IEEE Solid-State Circuits Magazine - Spring 2016 - 11
22
20
10
62
26
4
18
24
14 16
12
Analog
to
Digital
2
1
5
28
8
6
Digital
to
Analog
2
7
S
F
G
1
F
G
2
4
F
F
G
G
d
50
4
40
42
56
d
G
d
G
d
G
d
G
54
Addition
or Subtraction
G
d
1
1
F
2
2
F
4
4
F
8
8
F
16
16
F
60
52
110 KC
OSC.
M
S
58
Figure 3: The DSM proposed by Brahm in 1961.
according to the shaping function
(1 - z -1) N , where N denotes the order
(the number of integrators).
In 1981, an n-type metal-oxide-semiconductor (NMOS) implementation using
a single passive discrete-time integrator was reported [7], and in 1982, a patent was filed disclosing a loop with two
active switched-capacitor integrators
[8]. CMOS realizations followed in 1986
[9] and 1988 [10].
It is interesting that some authors
use the term "3 R modulator" and others
use the term " R 3 modulator" to refer to
the circuit. One argument in favor of the
former is that the loop first subtracts and
then accumulates.
sn
+
...
-
+
sn∗
A /D
-
...
D/A
Figure 4: A high-order DSM attributed to Ritchie.
ADC
Vin
Dout
t1
ta
tb
tc
t2
t
Figure 5: Oversampling to create correlation between consecutive samples.
Basic Operation
Suppose we wish to digitize the analog waveform shown in Figure 5.
A Nyquist-rate ADC would sample
and quantize Vin at t1 and t2, with
fs = 1/ (t 2 - t 1) slightly greater than
twice the signal bandwidth. In this
case, the samples at t1 and t2 exhibit
little correlation, and so do their quantization errors. On the other hand, if
we additionally sample and digitize
Vin at ta, tb, and tc, we create correlated quantization errors between
consecutive samples. From another
perspective, if the signal changes
slowly enough from t 1 to t a, then
IEEE SOLID-STATE CIRCUITS MAGAZINE
S P R I N G 2 0 16
11
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
IEEE Solid-State Circuits Magazine - Spring 2016 - Cover1
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IEEE Solid-State Circuits Magazine - Spring 2016 - 1
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IEEE Solid-State Circuits Magazine - Spring 2016 - Cover3
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