IEEE Solid-State Circuits Magazine - Spring 2016 - 13

Formulation of Noise Shaping
Let us examine how the quantization noise introduced by the quantizer in Figure 8(a) propagates to the
output. We assume a discrete-time
integrator and express its output as
u (kTs) = u [(k - 1) Ts] + g [(k - 1) Ts],
where g [(k - 1) Ts] = x [(k - 1) Ts] y [(k - 1) Ts] . The quantizer output
is given by y (kTs) = u (kTs) + q (kTs),
and reaches the DAC output unchanged if the DAC is ideal. Substituting
for g [(k - 1) Ts] and for y [(k - 1) Ts],
we obtain
y (kTs) = u [(k - 1) Ts] + x [(k - 1) Ts]
- y [(k - 1) Ts] + q (kTs) .

(1)

Since u [(k - 1) Ts] - y [(k - 1) Ts] =-q
[(k - 1) Ts], we have
y (kTs) = x [(k - 1) Ts] + q (kTs)
- q [(k - 1) Ts] .

(2)

As expected, the output quantization noise is equal to the difference
between the quantization errors
incurred by two consecutive samples. Taking the z transform of both
sides yields
Y (z) = z -1 X (z) + (1 - z -1) Q (z) . (3)
The output thus contains the input
with no change but just a delay.
The quantization noise experiences
a 1 - z -1 transfer function. We say
the system provides a "signal transfer function" (STF) equal to z -1 and a
"noise transfer function" (NTF) equal
to 1 - z -1 .
To determine the output noise
spectrum, we replace z in 1 - z -1
with exp ( j~Ts) and multiply the
spectrum of q(t), S Q (f ), by |1 - exp
(- j~Ts) |2 = (2 sin rf Ts) 2 . Figure 8(b)
plots this noise-shaping function,
revealing that integrated quantization noise can be small if the input
signal bandwidth fB % fs /2. The
quantity M = (fs /2) /fB is called the
"oversampling ratio" (OSR) and signifies how far above the Nyquist
rate the system operates. The area
under the curve in Figure 8(b) from

1 - z -1
x

g

+

u

ADC

-
DAC

y

2

4

0

fB

(a)

fS
2
(b)

f

Figure 8: (a) First-order DSM for noise shaping calculations and (b) its noise-shaping function.

zero to f B is proportional to 1/M 3,
revealing the strong dependence of
the performance upon the oversampling ratio.
In addition to noise shaping, DSMs
provide two other advantages over
Nyquist-rate ADCs. First, for a given
amount of kT/C noise, the sampling
capacitors in the former can be smaller
than those in the latter by a factor of
M. This can be intuitively explained
by noting that the extra samples taken
in Figure 5 are eventually combined
with those at t1 and t2 (by means of
a "decimator"), benefiting from kT/C
noise (and op amp noise) averaging.
Second, the antialiasing filter in the
former has a more relaxed selectivity
than in the latter.

DSMs with Multibit Quantizers
In the spirit of Brahm's patent (Figure 3) and to lower the quantization
noise, we can digitize the integrator output with more than one bit
of resolution and feed the result to
a multibit DAC. Typically realized as
a flash stage, the quantizer injects
proportionally less noise as its resolution increases. The performance
of the system, however, is limited
by the DAC nonlinearity, as pointed
out by van de Plassche in 1979 [5].
In contrast to the two-level DAC
in Figure 7(a), a multibit DAC exhibits nonlinearity in its input-output
characteristic if its constituent components (resistors, capacitors, or current sources) have mismatches. This
phenomenon can be viewed in Figure
8(a) as an undesirable term subtracted by the DAC from x and hence indistinguishable from nonlinearity in the
input path.

The problem of DAC nonlinearity proves serious because DSMs
typically target high resolutions, at
which the "raw" device mismatches
produce considerable distortion. For
this reason, loops containing multibit DACs employ "dynamic element
matching" techniques to reduce this
nonlinearity [5].

Higher-Order DSMs
Another approach to reducing the
noise of the quantizer is to replace
it with another 3 R modulator [Figure 9(a)]. Here, the outer loop further shapes the quantization noise
of the inner loop, yielding a shaping
function of the form (1 - z -1) 2 for
the 1-b quantizer's noise. The area
under | 1 - z -1 | 2 from zero to fB is
now proportional to 1/M5, a marked
reduction compared to that of the
first-order loop.
Providing identical outputs, the two
DACs in Figure 9(a) can be merged,
resulting in the more compact architecture shown in Figure 9(b). Exemplified
by the implementation in Figure 9(c)
[10], this simple, robust topology is
the most commonly used DSM for
moderate-performance applications. It
can be shown that such imperfections
as capacitor mismatch, op amp offset,
op amp gain error, and comparator offset have much less impact here than
in, for example, pipelined ADCs. The
order of the loop can be increased
further by adding more integrators,
but instability becomes problematic,
requiring other measures.

Problem of Tones
As explained earlier, the average
output of a DSM tracks the input signal.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

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