IEEE Solid-State Circuits Magazine - Spring 2016 - 14

X (s )

+
-

Y (s )
-
DAC

DAC
(a)
+

X (s )

+
-

Y (s )
-
DAC
(b)

S2
C1 S3
S4
4

S1
In
n

S4
C1
S3
S2

C2
-+

S
3
S3
S2
2
C S4
C1

Out

C1 S4
S3
S2

VREF+
VREF-

VREF-
VREF+

(c)

Figure 9: (a) A second-order DSM, (b) the simplified architecture, and (c) a discrete-time
implementation.

Vin

C2
R2

-
+

CK
-
+

Figure 10: A simple second-order CTDSM.

What happens if Vin in Figure 2 is
constant? Since the loop is periodically clocked and Vin does not change
with time, we surmise that the output is also periodic. For example, if
Vin = 0.001VREF, then Dout consists of
one ONE and another 999 ZEROs so as
to produce such an average. Repeating with a period of 1000Ts, the output
therefore exhibits harmonics given
by mfs/1000, many of which can fall

S P R I N G 2 0 16

within the signal band. These "tones"
corrupt the digitized signal. The tones
tend to be smaller in magnitude in
higher-order loops or at higher oversampling ratios, but one must often
incorporate "dithering" to break their
periodicity and convert them to noise.

Continuous-Time DSMs
The evolution of DSMs has made a
360° turn over the years. The earliest

IEEE SOLID-STATE CIRCUITS MAGAZINE

designs, those by Brahm and Inose
et al., for example, employed continuous-time integrators, but, as switchedcapacitor techniques matured in CMOS
technology, discrete-time integrators
became more common. In the late
1990s, it was recognized that continuous-time integrators offer certain
advantages, and continuous-time DSMs
(CTDSMs) rapidly rose as a formidable
contender. It is important to note, however, that even CTDSMs are discretetime feedback loops, still facing tone
and stability issues.
Depicted in Figure 10 is a simple
CTDSM realization of a second-order
loop, where the current sources act as
1-b DACs. This arrangement provides
three advantages over its discrete-time
counterparts: 1) the sampling is performed by the comparator, obviating
the need for highly linear front-end
(bootstrapped) samplers, 2) the DSM
presents less input capacitance and
kickback noise, easing the demand on
the preceding circuit, and 3) the two
integrators naturally provide antialiasing filtering, simplifying the other filter stages in the signal path.
CTDSMs entail their own drawbacks. First, the jitter in the comparator clock modulates the amount
of charge delivered by the feedback DACs to the integrators. This
issue has been addressed by various techniques, e.g., the use of
switched-capacitor DACs [12]. Second, the integrator op amps must
have enough bandwidth to avoid
slewing, a difficult issue because the
comparator quantization noise traveling through the DACs and arriving at the integrators presents fast
changes. This translates to a greater
power consumption than that of op
amps in discrete-time DSMs. Third,
the signal-dependent delay of the
comparator, each time it approaches
metastability, also modulates the
DACs' outputs, leading to distortion.
The comparator must therefore be
designed for a short regeneration
time so that metastable states occur
infrequently enough to negligibly affect the signal. Fourth, the thermal
noise of R1 and I1 in Figure 10 limits
the performance.

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016