IEEE Solid-State Circuits Magazine - Spring 2016 - 15

branches that are driven by 25%duty-cycle local oscillator phases?
No, it does not. The steady-state
swing remains the same.

A
+
Iin

VAB

LO

LO
X
R1

C1

Y
C2

References

-
B
LO

Iin

V1

VAB

t

Figure 11: Steady-state waveforms in a commutated circuit.

Note on StrongArm Latch
In my article on the StrongArm latch
[13], I had traced the circuit to a 1992
paper by Kobayashi et al. The idea was
in fact filed for a patent by Madden
and Bowhill on 27 June 1988 in the
United States and by Kobayashi's coauthor, Nogami, in Japan on 13 July 1988.

Questions for the Reader
1) Explain in the time domain why
1-z -1 represents a high-pass function.
2) Explain why the comparator clock
jitter in a discrete-time SDM such
as that in Figure 9(c) is not critical.

Answers to Last Issue's Questions
1) The commutated capacitors of Figure 11 are placed at the antenna

port of a Global System for Mobile
Communication (GSM) receiver so
as to attenuate by 20 dB a 0-dBm
blocker at 20-MHz offset. What issues does such a circuit face?
Such an approach faces three
issues. First, from Smith's equation, the array must employ a large
capacitance to provide a small
bandwidth with a 50-Ω source resistance. Second, the on-resistance
of the switches must be about 5 Ω,
demanding a high power in the LO
drive circuitry. Third, the switches
experience a large voltage swing in
the presence of a 0-dBm blocker, exhibiting considerable nonlinearity.
2) Does V1 in Figure 11 change if the
circuit contains four capacitive

[1] H. Inose, Y. Yasuda, and J. Murakami, "A telemetering system by code
modulation-Δ-Σ modulation," IEEE Trans.
Space Electron. Telemetry, vol. 3, pp. 204-
209, Sept. 1962.
[2] C. B. Brahm, "Feedback integrated system," U.S. Patent 3,192,371, Sept. 1961.
[3] J. C. Candy, "A use of limit cycle oscillations to obtain robust analog-to-digital conversion," IEEE Trans. Commun.,
vol. COM-22, pp. 298-305, Mar. 1974.
[4] J. C. Candy, C. Y. Ching, and D. S. Alexander, "Using triangularly weighted
interpolation to get 13-bit PCM from
a sigma-delta modulator," IEEE Trans.
Commun., vol. COM-24, pp. 1268-1275,
Nov. 1976.
[5] R. van de Plassche, "A five-digit analogdigital converter," IEEE J. Solid-State
Circuits, vol. SSC-12, pp. 656-662, Dec.
1977.
[6] S. K. Tewksbury and R. W. Hallock, "Oversampled, linear and predictive noise-shaping coders of order N > 1," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 436-447, July
1978.
[7] T. Misawa, J. E. Iwersen, L. J. Loporcaro,
and J. G. Ruch, "Single-chip per channel
codec with filters utilizing Δ-Σ modulation," IEEE J. Solid-State Circuits, vol. 16,
pp. 333-342, Aug. 1981.
[8] K. Shenoi and B. Agrawal, "Delta-sigma
modulator with switch capacitor implementation," U.S. Patent 4,439,756, Jan.
1982.
[9] T. Hayashi, Y. Inabe, K. Uchimura, and T.
Kimura, "A multistage delta-sigma modulator without double integration loop,"
in ISSCC Dig. Tech. Papers, Feb. 1986, pp.
182-183.
[10] B. Boser and B. A. Wooley, "The design
of sigma-delta modulation analog-todigital converters," IEEE J. Solid-State
Circuits, vol. 23, pp. 1298-1308, Dec.
1988.
[11] H. A. Spang and P. M. Schultheiss, "Reduction of quantizing noise by use of feedback," IRE Trans. Commun. Syst., vol. 10,
pp. 373-380, Dec. 1962.
[12] M. Ortmann, F. Gerfers, and Y. Manoli,
"Jitter insensitive feedback DAC for continuous-time ΣΔ modulators," in Proc. Int.
Conf. Electronics, Circuits, and Systems,
2001, pp. 1049-1052.
[13] B. Razavi, "The StrongArm latch," IEEE
Solid-State Circuits Mag., vol. 7, no. 2, pp.
12-17, Spring 2015.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

15
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
