Chulwoo Kim, Hyun-Woo Lee, and Junyoung Song Memory Interfaces Past, present, and future I ver the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known "memory wall" problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from Digital Object Identifier 10.1109/MSSC.2016.2546659 Date of publication: 21 June 2016 1943-0582/16©2016IEEE single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM? In this article, we first consider important DRAM interface design issues of the past and present. Then, by reviewing the development of high-performance DRAM technologies in conjunction with the DRAM interface IEEE SOLID-STATE CIRCUITS MAGAZINE S P R I N G 2 0 16 23