IEEE Solid-State Circuits Magazine - Spring 2016 - 24
Maximum Data Rate per Pin (Gb/s/Pin)
While this degradation is a function of capacitive loading, it is just
as much a function of the temporal distribution of that capacitance
and the resulting signal reflections.
High-bandwidth memory (HBM) has
reached I/O bandwidth of 128 GB/s
due to the advancements of throughsilicon via (TSV) and packaging technologies, even though per-pin I/O
speed is only 1 Gb/s.
12
10
8
6
4
Past Challenges and Innovations:
The First Turning Point
2
In DDR2 SDRAM of the 1990s, three
key I/O technologies made it possible
to break the limitation of I/O speed:
delay-locked loop (DLL), data strobing
(DQS), and source-synchronous clocking architectures, newly introduced in
Figure 1: The maximum data rate per pin of each subsequent DRAM product over the
DDR SDRAM. In synchronous DRAM,
years, beginning in the late 1990s.
the output (READ) data is aligned with
environment for various system
an external clock after tAC, which
within DRAM standards like LPDDR4
applications, we cautiously predict
consists of internal clock delay (tD1)
and GDDR5.
the next generation of DRAM sysand timing delay from the internal
Interestingly, as power consumptem architecture.
clock to the outputted data (tD2).
tion has become more crucial-with
Because tAC is a function of process,
mobile devices serving as a driving
Background
voltage, and temperature (PVT), READ
force of DRAM technology-targets
Beginning in the late 1990s as these
data availability at the memory-confor LPDDR4 have imposed the chalnew technologies developed, two
trol unit (MCU) exhibits both static
lenge to double the throughput of its
DRAMs are of particular interest:
and dynamic variability. When the
predecessor, while simultaneously
direct Rambus DRAM [1] and DDR
MCU attempts to capture all incoming
reducing energy per bit (if possible).
SDRAM [2]. The history of high-speed
data bits simultaneously, the valid
Conversely, in module-based system
DRAM starts from the new technolodata window disappears and causes
applications, the operating speed of
gies employed in these two DRAMs.
a failure to capture the data without
DRAM is a function of the number of
As shown in Figure 1, the per-pin
DLL for removing the tAC variation, as
modules on the data bus, implying a
data rate of DRAM products has condescribed in Figure 3; the conceptual
significant operating speed limitation
tinuously increased, from 400 Mb/s/
block diagram of clocking with DLL is
associated with multiple dual in-line
pin to 12 Gb/s/pin currently. There
shown in Figure 4 [6], [7].
memory modules (DIMMs) per chanare two turning points in this trend
While skew between parallel data
nel (DPC), as shown in Figure 2 [4].
toward rapidly increasing
bits was addressed by the
I/O speed: first, when SDRAM
retiming just mentioned,
transitioned from an SDR
the arrival time of the parDDR4 2133 System
clocking architecture to a DDR
allel READ data as a whole
remained somewhat unprearchitecture and, second,
1 DPC
2 DPC
3 DPC
dictable-partly as a function
w h e n GDDR x r e ac h e d
of off-chip delays through the
7 Gb/s/pin [3]. By investigating
99.0
platform-dependent chip-tothe technologies utilized to
chip transmission line and
transition DRAM I/O from SDR
82.0
17%
partly as a function of on-chip
to DDR over a decade ago, we
27%
71.8
delays through gates and bufcan understand some of the
fers. As a result, the READ data
past challenges that had to
valid window would close
be overcome. In more recent
as time-of-flight variation
history, new I/O features to
0 10 20 30 40 50 60 70 80 90 100
introduced skew between the
facilitate further bandwidth
phase of the transmitted data
extension have been adopted Figure 2: Speed versus the number of DIMMs within the interface.
24
S P R I N G 2 0 16
D 3
LP DR
D 4
LP DR
D 1
LP DR
D 2
D
LP R
D 3
D
G R4
D
D
G R1
D
D
G R2
D
D
G R3
D
D
G R4
D
D
G R5
D
D
R
5X
2
R
D
D
R
D
D
D
D
R
1
0
IEEE SOLID-STATE CIRCUITS MAGAZINE
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