IEEE Solid-State Circuits Magazine - Spring 2016 - 25

and the reference clock, as illustrated
in Figure 5(a).
To compensate for the unpredictable variation in channel flight times,
a source-synchronous clocking architecture was adopted, and two pins
per byte were added, to transmit a
differential, periodic DQS signal in
parallel with the random data (DQ),
as shown in Figure 5(b). Referencing the READ DQ to the DQS signal
mitigated sensitivity to time of flight,
and the phase relationship between
data and the system clock no longer
limited performance. To strobe the
optimum data sampling point during
READ operation, the controller uses
DLL or phase-locked-loop (PLL) to
make a 90° lagged signal. As shown
in Figure 6, at the point of transmission, the WRITE data is center aligned
with the DQS signal while the READ
data is edge aligned with the DQS [8].
This is called a source-synchronous
scheme [9]-[11].
One final early innovation to
decouple I/O speed from the much
slower memory-array cycle time was
the prefetch scheme, through which
the array transfers 2-N bits of data
at a time, where N represents the
number of column accesses. Initially, DDR SDRAM started with a
2-b prefetch scheme to support the
desired I/O operating speed. Since
then, the amount of prefetched data
has grown to support subsequent
increases in effective I/O bandwidth.
To summarize: the combination of
DLL-based tAC compensation, sourcesynchronous DQS, and prefetch
features incorporated into the early

CK
DDR Case

tACPVT1
DataPVT1
tACPVT1
DataPVT2

DataPVT1 + DataPVT2
No Valid Data Window Without DLL
DDR Case
DataPVT1
DataPVT2
DataPVT1 + DataPVT2
Valid Data Window with DLL

Figure 3: High-speed timing sensitivity to PVT variations without and with DLL.
Clock Tree + DLL
Delay
Buffer
PD

Buffer

CK
tD1

DRAM Core

tD1

tD2
tD2
DQ

Buffer
Data Sampler

DRAM Core Control Logic

Data Sampler

Buffer

Figure 4: A simplified DRAM architecture with DLL. PD: phase detector.

CK

CK

DQ

DQ

DQS

DQS

DQ

DQ
tFLT

tFLT

DQ

DQ

Flight time = tFLT′
Flight time = tFLT′
DQS
CK
(a)

Flight time = tFLT′
(b)

Figure 5: A timing diagram (a) without and (b) with DQS.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

25



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016

IEEE Solid-State Circuits Magazine - Spring 2016 - Cover1
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IEEE Solid-State Circuits Magazine - Spring 2016 - 1
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