IEEE Solid-State Circuits Magazine - Spring 2016 - 26

DRAM architectures enabled
the transition from SDR to
DDR, doubling the effective
data rate.

Otherwise, the DQS is
directly connected to the
data samplers to capture the
DQS
data, which come from the
MCU as depicted in Figure 7.
Center Aligned
Recent Challenges and
There is no replica delay to
WRITE Data
Innovations: The Second
match the DQS delay path.
Turning Point
The DQS path delay has
Edge Aligned
High-speed DRAMs such as
to be compensated at the
READ Data
DDR4, LPDDR4, and GDDR5
MCU, by the timing paramare used in many applications
eter, tDQS2DQ. The MCU
today, with targeted data rates
calculates tDQS2DQ (the
of 3.2 Gb/s, 4.267 Gb/s, and
DQS path delay) during a
7 Gb/s, respectively. As was Figure 6: The timing diagram between DQS and WRITE/READ data.
training process. Basically,
the case in overcoming the
tDQS2DQ is moved from
earlier challenges, modern
DRAM to the MCU, allowing
DRAMs have had to innovate
improvement by using the
called READ latency (RL). For writing
to continue scaling. Key technologies
application-specific integrated cirdata, the WRITE latency (WL) should
enabling today's architectures include
cuit (ASIC) process technology, which
be defined.
unmatched DQ-to-DQS clocking, the
is better than that of DRAM.
Speaking of operations inside of
use of on-die termination (ODT) for
So it seems that the timing variDRAM, the data issued by the MCU
the reflection-dominated COMMAND/
ance of tDQS2DQ according to VDD
ADDDRESS (C/A) interface, a variety of
or temperature is the key parameter,
is captured by DQS when the WRITE
new channel topologies designed to
operation is in progress after the WL.
but the frequent training sequence
support higher speeds, and multiphase
The phase relationship between DQS
removes this penalty. This training
clocking used to relax timing requireand DQs in the DDR4 SDRAM is mainis WRITE training. By using WRITE
training in an unmatched clocking
ments [9]-[11].
tained at the transmit side of the
architecture, the additional matching
MCU. However, the phase relationUnmatched Clocking
delay logics employed in DQ paths
ship between them for LPDDR4 and
The first common feature in highare removed. However, the additional
GDDR5 is determined by a training
WRITE training process is mandatory.
speed DRAM interfaces is an unprocess controlled by an applications
The advantage of this method is that
matched clocking architecture for
processor or a graphics processthe receiver inside of DRAM becomes
DQs. In synchronous DRAM, most oping unit (GPU). To match the paths
simpler, and the skews among DQs
erations are synchronized with a clock
among them, each DQ should have
are removed by the WRITE training
external to DRAM. Therefore, the READ
some delay modeling to compensate
data coming from the DRAM should
procedure. Furthermore, the decithe DQS path; this is the matched
be addressed in terms of clock cycles
sion-feedback equalizer (DFE) can be
clocking architecture.

Matched Type

Unmatched Type
tDQS2DQ
DQ

DQS

DQ/VREFDQ

DQ/VREFDQ
tDQSreplica

DQS/DQSF

DQS/DQSF
tDQS

Figure 7: (a) Unmatched and (b) matched clocking schemes.

S P R I N G 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

tDQS

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016