IEEE Solid-State Circuits Magazine - Spring 2016 - 27

easily employed in the DRAM with the
unmatched clocking scheme. Hence,
the timing margin between DQ and
DQS is increased. An example of the DQ
receiver of an unmatched clocking architecture with DFE is depicted in Figure 8.

High-speed DRAMs such as DDR4, LPDDR4, and
GDDR5 are used in many applications today,
with targeted data rates of 3.2 Gb/s, 4.267 Gb/s,
and 7 Gb/s, respectively.

ODT and C/A Interface
The second common feature is ODT and
C/A interface. The ODT is a very efficient way to improve signal integrity.
However, it consumes a huge amount
of power when the ODT is enabled.
While LPDDR4 and GDDR5 have
ODTs in DRAM, for DDR4 with a flyby topology, the C/A termination
logic is as shown in Figure 9. The
termination resistors are connected

DQ

outside of DRAM in DIMM. Because
of stub, multidrop, and so on, signal integrity worsens. Therefore, the
signal integrity of C/A in LPDDR4
and GDDR5 is better than in DDR4.
Because of the heavy loading due to
parallel connection of C/A pins, additional buffering is required in the
DIMM; this is called registered DIMM.

DFE

On the other hand, the C/A pins in
GDDR5 with the clamshell configuration shown in Figure 10 are connected
by a point-to-point method. In this
case, when the termination resistance
is 2*ZQ for each chip, the parallel
resistance becomes ZQ. Therefore,
the termination resistance is preserved in the clamshell configuration.

Fly-by Topology

DRAM
1

CLK0

VTT
DRAM
2

DRAM
7

DFE

DRAM
8
DQ and DQS

CLK90
DFE

Figure 8: An example of the DQ receiver of an unmatched clocking
architecture used in GDDR5 and LPDDR4.

8
D

R

AM

7

GDDR5 SGRAM x16

Memory Controller

Memory Controller

DQ x16

AM

Clamshell Mode (x16)

GDDR5 SGRAM x32

Command/Address

R

AM
R

Figure 9: The fly-by topology for DDR4.

Normal Mode (x32)

DQ x16

D

D

R

CLK270

D

AM

1

2

DFE

VREFDQ

Skew

CLK180

CLK, CMD, Address

DQ x16
Command/Address
DQ x16
GDDR5 SGRAM x16

Figure 10: Two configurations for GDDR5.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

27



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016

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