IEEE Solid-State Circuits Magazine - Spring 2016 - 28
Finally, DDR4 needs some breakthroughs to overcome the speed limit
on the C/A side, and gear-down mode
is employed for enlarging margin on
the C/A side [9]. The C/A and I/O rate
comparisons for DDR4, LPDDR4, and
GDDR5 are summarized in Table 1.
TAbLE 1. CoMPARISonS of DDR4, LPDDR4, AnD GDDR5.
GRoUP
ITEM
DDR4
LPDDR4
GDDR5
Data rate
Per pin
~3.2 Gb/s
~4.266 Gb/s
~9 Gb/s
Interface
Data sampling
Matched
Unmatched
Unmatched
DLL / PLL
DLL
-
-
Type
POD
LVSTL
POD
DQ termination
On die (VDDQ)
On die (VDDQ)
On die (VDDQ)
C/A termination
External (CTT)
On Die (VSSQ)
On die (VDDQ)
DQ WRITE
Per byte
Per pin
Per pin
DQ READ
-
Per pin
Per pin
DQ
Internal
Internal
Internal (or external)
Training
VREF
generation
POD: pseudo-open drain; LVSTL: low-voltage swing terminated logic; CTT: center-tab termination.
However, there is one more important thing that should be considered
about the operating frequency of C/A.
Even if the I/O speed is two or four
times faster than the C/A speed with
the help of a serializer, the operating
frequency inside of DRAM after serial-
izing is divided by tCCD. So the internal data processing time becomes 1/
(tCK*tCCD). On the DRAM and controller sides, the SDR command interface
with half the rate of the I/O speed is
adopted, reducing the design complexity as well as the power consumption.
Removal of DLL
The third common feature in the highspeed DRAM interface is the removal of
DLL. The main goal of DLL used in DDRx
SDRAM is tAC compensation. However,
as this is done by a READ training process during the initialization procedure, the DLL is removed in LPDDR4
and GDDR5. In GDDR5, even though
PLL is an optional feature [11], DRAM
with PLL is not showing a comparable
performance against DRAM with DLL
because the PLL fabricated in a DRAM
process technology is not successful because low-cost DRAM processes
result in wide process variations.
Command
To State Machine
Address
Address Decoder
Address Decoder
CK, /CK
Rx
To EDC Pin
0
90
MUX
180
270
RVS
Rx
WCK, /WCK
DCC
ICLK/QCLK
(0, 90, 180, 270)
DQ<0:7>
DQ<8:15>
Rx
RVS: Reverse
EDC: Error Detection Code
DCC: Duty Cycle Corrector
MUX: Multiplexer
DRAM
Core
Tx
ICLK/QCLK
(0, 90, 180, 270)
Pipe Registers
Figure 11: A block diagram for GDDR5 clocking architecture. RX: receive; Tx: transmit.
28
S P R I N G 2 0 16
IEEE SOLID-STATE CIRCUITS MAGAZINE
ICLK/QCLK
(0, 90, 180, 270)
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