IEEE Solid-State Circuits Magazine - Spring 2016 - 29

Finally, the GDDR5 that we can
buy now does not include PLL or DLL.
However, DDR4 could not exclude
DLL because of the multidrop channel issue-even though DLL burns a
lot of power and increases the length
of clock delay. To remove the DLL or
PLL, the READ training process is mandatory. Because the READ timing varies depending on the location of the
module, accomplishing the READ training process in the multidrop channel
is complex. By getting rid of DLL, the
clock path is shortened and simplified.

an additional challenge. Therefore,
the solution for high-speed operation of DRAM is a parallelism method
of using a divided clock to reduce
the clock frequency to a half or quarter. The routing lines for clocks are
doubled, and it is called a four-phase
clocking scheme.

DRAM PAD and Tx

In the case of the LPDDR4 interface,
the channel length of package on package (PoP) is very short, as shown in
Figure 12. Three types of DRAMs-PoP
for LPDDRx, multidrop for DDR4, and
point-to-point on printed circuit board
(PCB) for GDDR5-have different types
of interfaces, as described earlier in

Bond Wire
PKG via
PKG Trace

Clocking Architectures of
LPDDR4 and GDDR5
To understand the latest advances
in high-speed DRAM, it is helpful
to see the clocking architectures of
LPDDR4 and GDDR5.
Figure 11 shows the block diagram
for the GDDR5 clocking architecture.
There are COMMAND, ADDRESS, CKs,
WCKs, and DQs. The COMMAND signals are sampled at a single data rate,
and the ADDRESS signals are sampled
at DDR of CK to reduce the pin counts.
While most synchronous DRAMs have
DQS and /DQS for writing and reading
operations, in GDDR5, there is a pair
of WCKs for writing data instead of
WDQS (DQS for WRITE). While the DQS
only runs when READ or WRITE operation is in progress, the WCK is a kind
of free running for READ and WRITE
operations, and it can be stopped
during power down or self-refresh.
Also, the frequency of WCK is twice
that of CK.
We can see something very interesting in the Figure 11 block diagram. There is no DLL for retiming or
PLL for regenerating the clock. The
only divider is the circuit, which can
handle the clock signal. This is the
key clocking scheme for GDDR5 that
makes it simple and robust in the
real-system applications. It enables
operation as fast as 8 Gb/s without
additional power consumption drain
by DLL or PLL. In the case of 8 Gb/s,
it is very difficult to manipulate signals having only a 125-ps high pulse
period in the DRAM process. Moreover, the lowered supply voltage is

AP Pad and Rx

Total Channel Path
Bump

Solder Ball

Figure 12: A PoP interface.

Channel A (X16DQ)
X8 DQ Side

CA Side

X8 DQ Side

Bank

Bank

Bank

Bank

Bank

Bank

Bank

Bank

Bank

Bank

BANK

Bank

Bank

Bank

Bank

Bank

X8 DQ Side

CA Side

X8 DQ Side

Channel B (X16 DQ)
DATA (with GIO) Path

Clock Tree

Figure 13: The chip architecture of LPDDR4.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016

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