IEEE Solid-State Circuits Magazine - Spring 2016 - 30

TAbLE 2. THE PoWER REDUCTIon SCHEME foR LPDDR4.
ITEM

ConDITIon

IDD MoDE

REDUCTIon fACToR

REDUCTIon RATIo

Page size

4k B à 2k B

IDD0

IPAGE

~20%

C/A pin reduction

10 C/A à 6 C/A

IDD2N and IDD3N

IRX

~20%

Short GIO

Two-channel configuration

IDD4R/W

IGIO

~10%

Short clock tree

Two-channel configuration

IDD0, 1, 3, 4

ICLOCK

~5%

tIS tIH
tISCS
CK_c

CK_c

CK_t

CK_t

CS

CS

CS

CS

CS

tIHCS

tISCA
CA
CMD

Valid

Valid

Valid

DSEL

Valid

COMMAND

Valid

DSEL

Valid

Valid

Valid

COMMAND

CS
tIHCA

CA
CMD

DSEL

DSEL

(b)

(a)
Figure 14: The timing diagram of (a) LPDDR4 and (b) LPDDR3.

TSV
DRAM Core Die
DRAM Core Die

Package
DRAM

DRAM Core Die

Substrate

DRAM Core Die

Ball Grid Array
Package

Base (Logic) Die
u-Bump

GDDR5x

Type

HBM

32 b

I/O Width

1,024 b

12 Gb/s
(Up to 16 Gb/s)

B/W per Pin

1 Gb/s
(Up to 2 Gb/s)

384 Gb/s
(512 Gb/s)

Bandwidth

1.35 V

Voltage

512 Gb/s
(1 Tb/s)
1.3 V

Figure 15: A comparison of GDDR5x and HbM. (a) GDDR5 and (b) HbM configuration and (c) a comparison table.

the article. In LPDDR4, which is shown
in Figure 13, the peripheral blocks are
located at both the top and bottom
sides, which is referred to as a dualchannel architecture. Therefore, the
I/O length is shorter than for LPDDR3.
Each channel block has a C/A block
and a ×16 DQ side.
The power reduction scheme for
LPDDR4 is summarized in Table 2. The
major items are page-size reduction,
pin reduction from ten to six, short
global I/O (GIO), and a short clock
tree. Receive power can be reduced by
pin-count reduction. In the case of the

30

S P R I N G 2 0 16

clock network, its power is reduced by
5% due to the short clock tree. Even
though VDD is reduced only by 100 mV,
because of the low-power architecture,
the total power savings is more than
10%. However, due to the dual channel,
the standby current, such as IDD2N or
3N, is almost doubled compared to the
single-channel counterpart.
Figure 14(a) and (b) compares the signaling between LPDDR3 and LPDDR4.
The speed limitation of the C/A pins is
lower than the DQ pins. While the timing margin of DQs using the unmatched
clocking scheme is increased by the

IEEE SOLID-STATE CIRCUITS MAGAZINE

training sequence, changing the C/A
pins from DDR to SDR increases the
timing margin of C/A, including the
decoding timing margin.

Future High-Performance
DRAM Interfaces
Next-generation DRAMs such as
GDDR5x, HBMx, and hybrid memory
cube (HMC) are continually breaking the limits of DRAM bandwidth.
There is no clear winner, as no one
yet owns the high-end DRAM market.
GDDR5x, which was initially expected to operate at about 12 Gb/s, can give



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016

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