IEEE Solid-State Circuits Magazine - Spring 2016 - 31

1.6X Shorter

2X Shorter

Sequential
Write 12% Random
Write 18%

110 mm

Random
Read 42%

55 mm

90 mm

55 mm

GDDR5 Configuration (x512)

Mobile AP

HBM Configuration

Figure 17: The DRAM state ratio in a mobile operating system.

Figure 16: Configuration examples for (a) GDDR5x and (b) HbM.

a cost-effective solution. By minimizing the changes from its predecessor
(GDDR5), GDDR5x has a compatibility
advantage. The key I/O technology of
GDDR5x is quad-data rate, which generates eight-phase clocks without increasing the frequency of WCK [12] by
manipulating the PLL (or DLL). Also,
the package form factor is changed to
reduce CIO. The actual operating frequency of GDDR5x depends greatly on
the performance of the PLL.
In fact, the performance of the transistor from the DRAM process is slower
than the ASIC process, and sometimes
the transistor performance is degraded
by the high-temperature memory fabrication. Some DRAM designers are
skeptical that good PLL for GDDR5 can
be produced in a DRAM process and
are instead focusing on developing
HBM as an alternative. Comparisons
between them are shown in Figure 15,
and their configurations are compared
in Figure 16.
HBM architectures show the highest bandwidth up to now. However,
HBMs are mounted on a silicon interposer along with the GPU (in the case
of graphics cards). Therefore, due to
the limited size of the silicon interposer, density is limited; the cost of
the silicon interposer is also a challenge. Because of this, use of HBM is
limited to density- and cost-insensitive applications. The density of HBM
can be increased by stacking, such as
an eight-level stack.
HMC is also a TSV-based high-bandwidth memory. TSV-based DRAMs are

Sequential
Read 28%

compared in Table 3. Among them,
which is most promising for the near
future? Let us think about this question by considering the requirements
of future DRAM.
Future multidata-rate DRAM will
need some new features to increase
the bandwidth, and some solutions
are now being introduced, such as
parallelism and efficient control of
refresh [12]-[15]. Before going further toward devising a way to boost
the I/O speed, we need to understand the performance changes and
the penalty of power dissipation on
system applications.
For DRAMs in system applications, even though the key opera-

tions of DRAM are WRITE and READ,
the most important operations to
achieve high performance are activating and precharging to access
different bank or row address. Figure 17 shows the ratio of the DRAM
state in mobile applications [16].
For only very short periods of time
(such as the burst length, which is
normally 16 or 32 for LPDDR4), the
data come out or are issued. Therefore, the asynchronous parameters
in DRAM-such as tRAS, tRP, tRFC,
and tRCD-are crucial, and they
should be reduced to increase the
performance in system applications.
When the I/O speed is doubled,
will the system performance also be

TAbLE 3. A CoMPARISon of TSV-STACkED DRAM: HbM, HMC, AnD WIDE I/o.
ITEM

HMC

HbM

WIDE I/o

Application

Servers

Graphics
computing

Smartphone

Interface

Point-to-point (SERDES)

Parallel via TSV

Per-pin speed

10, 12.5, or 15 Gb/s

Up to 2 Gb/s

Up to 1066 Mb/s

JEDEC Standard

TAbLE 4. A PERfoRMAnCE CHECk ACCoRDInG To I/o AnD tRfC.
ITEM

DDR3 bASE

GDDR5M bASE

Configuration

X16, eight
pieces

X16, eight
piecess

X16, eight
pieces

VDD

1.35 V

Per-pin speed

1.8 Gb/s

3.6 Gb/s

tRFC setting

237 ns

146 ns

235 ns

120 ns

Normalized performance

100%

108.35%

118.78%

130.15%

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016