IEEE Solid-State Circuits Magazine - Spring 2016 - 32

5.26E-04

5.28E-12

5.00E-04
4.00E-04

5.20E-12
5.00E-12

4.10E-04

3.00E-04

4.80E-12

4.61E-12

2.00E-04

4.60E-12

1.00E-04

4.40E-12

0.00E+00

4.20E-12

1066
2133
With 2 Gb DDR3 SDRAM

100

5.40E-12
Burst Read Energy (J/b)

Max. Random Read Energy (J/b)

6.00E-04

5 cm
1.8 cm

1

0.83
2.4 Gb/s

Channel Length
Operating Data Rate

mance improvement is achieved only
by reducing tRFC.
As proven by CPUs that use multicores to increase performance, DRAM
can increase the I/O bandwidth by
employing multichannel and multi-I/O
as well. For example, the I/O speed of
HBM is 500 MHz, but the bandwidth of
HBM is 128 GB/s [5] due to multi-I/O.
To improve the performance of
DRAM, the channel length has to be

Device

Interposer
Printed Circuit Board

Channel
Insertion Loss

Group
Pulse Response
at 10 GHz, 810 mV

Type

at 10 GHz

Maximum
Channel Length

PCB

≈ -3 dB

50 mm
(12 mm PKG +
38 mm PCB)

MCM

> -1 dB

> -1 dB

Type

Main Cursor
at 10 GHz

PCB

460 mV

20 mV

MCM

580 mV

16 mV

Figure 20: The features of an MCM channel and configuration.

32

S P R I N G 2 0 16

0.083
12 Gb/s

Figure 19: The I/o speed and channel length.

DRAM

Group

8 Gb/s

0.1

Multichip Module (MCM)
GPU

0.25

0.01

Figure 18: The power consumption according to the operating
mode and I/o speed.

doubled? As can be seen in Table 4,
even though I/O speed is doubled
from 1.6 Gb/s to 3.2 Gb/s, only about a
19% increase in system performance is
achieved. In DDR3 SDRAM, the energy
consumption of random access is
increased by about 24% when the I/O
speed is doubled, even though the I/O
scheme is exactly same, as shown in
Figure 18. By contrast, with the same
I/O speed, as much as an 8% perfor-

15 cm
10

IEEE SOLID-STATE CIRCUITS MAGAZINE

Crosstalk

reduced if we want to increase the I/O
speed. For point-to-point interface
and DIMM, shorter channel length is
more suitable for higher operating
speeds, as shown in Figure 19. GDDR5
having a point-to-point interface is
employed in a less than 7-cm channel
environment, and DIMM consisting of
DDR4 is slotted in about a 15-cm channel environment. The most recent
graphics memory, GDDR5x, has much
less channel length in graphics card
applications. Therefore, the ultimate
channel-length target is 0.
This small length channel can be
realized in wide I/O DRAM, HBM, and
HMC. The direct contact by TSV or
through-mold via (TMV) is considered in wide I/O DRAM. In the case
of interfaces with more than 1,024
I/Os, HBM is mounted on a silicon
interposer with a processor, and the
number of HBMs is generally limited
to four in one silicon interposer.
Moreover, the wide I/O DRAM is
more restricted in terms of density
because the number of dies that will
be stacked on a processor is more
limited compared to the number of
HBMs on the silicon interposer.
Even though both wide I/O and
HBM increase bandwidth significantly, they cannot provide enough
capacity in certain application systems. Therefore, we need to configure
a new memory system architecture
that has far and near memory analogous to computers with DRAM for
fast access and hard-drive disk for
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
