IEEE Solid-State Circuits Magazine - Spring 2016 - 33

DRAM CA /CLK
ODT (R = 8*ZQ)

3DS
DRAM

CPU
TSV
Slow Side
Multidrop

DRAM CA /CLK
Buffer

Fast Side
(Multirank)

CA and CLK

(a)

(b)

Figure 21: (a) A two-tier memory system architecture with 3DS-DIMM and (b) a C/A-oDT configuration.

large capacity. In this tiered memory
system architecture, memory management is very complex, as the level
of memory hierarchy gets increasingly deeper. The HBM and processor
are mounted on one silicon interposer, so the test cost, yield, and
memory cost are big issues, and the
fault-recovery scheme is mandatory.
Early GDDR5x with multichip module (MCM) for better performance,
which has a very short channel length,
can be a good solution, as shown in Figure 20. However, the high cost of this
system is a bottleneck for MCMs to be
utilized in graphics-card applications.
LPDDRx configured in the PoP has
a short channel length, and the speed
of LPDDR4 has reached 4,266 Mb/s.
LPDDR4 is configured with an edge
pad type because they are generally
configured with a multichip package
(MCP). Because of the dual-channel
architecture, standby current is doubled. In general, IDD0 and IDD3N are
essential IDD modes because LPDDR4
is accessed in an interleaved manner
with a closed-row policy. To make
×32 data width using a single channel, the center PAD type is required
for faster cell access. With a center
PAD using a redistribution layer (RDL)
configuration, single-channel and
×32 configurations are possible in
the next LPDDR4; this is also needed
for increasing the number of banks to
enhance accessibility.
To overcome the increased RLC due
to RDL, the TMV method is employed
in a PoP configuration, and the cost

of the package is less than the
HBM. Moreover, if LPDDR4 employs
GDDR5's clocking architecture with
auto-synch mode, then LPDDR4
can operate as fast as 7 Gb/s, just
like GDDR5.

and DRAM is reduced, and per-pin
I/O speed will be enhanced. The
distance between DIMM to DIMM is
reduced to almost zero by adopting
the 3DS DRAM configuration, but the
cost is increased. However, by remov-

Next-generation DRAMs such as GDDR5x, HBMx,
and hybrid memory cube (HMC) are continually
breaking the limits of DRAM bandwidth.
How can we improve the DDR4 in
the DIMM channel? Because of the flyby topology and the DIMM channel,
the I/O bandwidth is very limited,
unlike that for LPDDR4 or GDDR5.
To reduce the loading of DQs and
C/A, registered DIMM, load-reduced
DIMM, and fully buffered DIMM are
used. However, the cost of these are
higher than unbuffered DIMM. The
most important thing in the DIMM
channel is a cost-effective architecture. Therefore, DDR4 needs to focus
on increasing the effective bandwidth, not per-pin I/O speed. DDR4
needs to employ per-bank refresh, to
increase the number of banks, and
to adopt the C/A-ODT or gear-down
mode as mandatory. Also, in system
environments, the DDR4 interface
should reduce the number of multidrop positions. If we remove the far
side of the DIMM channel by employing three-dimensional stacked (3DS)DIMM, the distance between the MCU

ing the DQ buffers in DIMM, the cost
is offset. Finally, we can expect the
DIMM configuration with DDR4, as in
Figure 21.

Conclusions
Summarizing the requirements for
future memory systems, the key
topics are the effective bandwidth;
increasing the number of banks; or
using pseudobanks, per-bank refresh,
3DS technologies, wide I/O with TSV
or TMV, and multitier memory system
architectures. Table 5 summarizes these
key features.
We cautiously predict that GDDR5
can be merged with LPDDR4, and this
LPDDR5 will be available in the future.
LPDDR5 will be up to 7~8 Gb/s, with
GDDR5's clocking architecture, a single channel, 32 banks and ×32/channel MCP with RDL, error-correcting
code, complex COMMAND, a reduced
C/A rate, 3DS, and TMV. Also, for the
next DDR4, several technologies are

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016