IEEE Solid-State Circuits Magazine - Spring 2016 - 34

TAbLE 5. REQUIRED fEATURES foR fUTURE MEMoRy.
REQUIRED fEATURE
foR C/A

REQUIRED fEATURE
foR DQ

REQUIRED fEATURE
EXCEPT foR I/o

ODT

ODT

Per-bank refresh

Reduced operating rate

Removal of DLL and READ/WRITE
training

Increased number of
banks

Training

Multiphase clocking

3DS technology

Reduced pin counts

Unmatched clocking and DFE

MCM and TMV

Complex command

Increased I/O width

RDL

Divided C/A decoding

Cycle-redundancy/error checking

Reduced channel length

good candidates to be utilized; the
doubled-bank, per-bank refresh; 3DS;
reduced channel length; C/A-ODT;
and an unmatched clocking scheme
that enables simple DFEs. In addition, DLL will be included for a while
because of multidrop topology.
LPDDR4, GDDR5x, DDR4, HBM,
HMC, and wide-I/O DRAM will continue
to develop in the meantime because
of different interface architectures. In
terms of performance, because HBM
and HMC show the highest bandwidth
up to now, they have the potential to
be chosen as one of the next DRAMs.
However, their high cost is a very
major concern, and it will require more
time for HBM and HMC to be widely
adopted in real applications.
Clearly, we are now at the turning
point of jumping to the next DRAM, to
do so, the effective bandwidth will be
key. This will be based on DRAM architecture, efficient bank management,
improvement of the C/A bandwidth,
improved channel environments, and
more efficient power management.

References

[1] T. H. Lee,K. S. Donnelly, J. T. C. Ho, J. Zerbe, M.
G. Johnson, and T. Ishikawa. "A 2.5V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s
DRAM," IEEE J. Solid-State Circuits, vol. 29, no.
12, pp. 1491-1496, Dec. 1994.
[2] Y. Takai, M. Nagase, M. Kitamura, Y. Koshikawa, N. Yoshida, Y. Kobayashi, T.
Obara, Y. Fukuzo, and H. Watanabe,. "250
Mbyte/s synchronous DRAM using a
3-stage-pipelined architecture," IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 426-431,
Apr. 1994.
[3] R. Kho; D. Boursin, M. Brox, P. Gregorius,
H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M.
Plan, M. Richter, I. Russell, K. Schiller, R.
Schneider, K. Swaminathan, B. Weber, J.
Weber, I. Bormann, F. Funfrock, M. Gjukic,

34

S P R I N G 2 0 16

W. Spirkl, H. Steffens, J. Weller, and T. Hein,
"75nm 7Gb/s/pin 1Gb GDDR5 graphics
memory device with bandwidth-improvement techniques," in Proc. IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers, 2009,
pp. 134-135.
[4] [Online]. Available: http://frankdenneman.
n l / 2015/02/ 25/m e m o r y - d e e p - d i v e ddr4/
[5] D. U. Lee, K. W. Kim, K. W. Kim, K. S. Lee, S.
J. Byeon, J. H. Kim, J. H. Cho, J. Lee, and J. H.
Chun "A 1.2 V 8 Gb 8-channel 128 GB/s highbandwidth memory (HBM) stacked DRAM
with effective I/O test circuits," IEEE J. SolidState Circuits, vol. 50, no. 1, pp. 191-203,
Jan. 2015.
[6] C. Kim, H. W. Lee, and J. Song, High Bandwidth Memory Interface. New York: Springer, 2013.
[7] H. W. Lee and C. Kim, "Survey and analysis
of delay-locked loops used in DRAM interfaces," IEEE Trans. VLSI Syst., vol. 22, no. 4,
pp. 701-711, Apr. 2014.
[8] [Online]. Available: https://www.micron.
com/~/media/documents/products/datasheet/dram/ddr1/1gb_ddr.pdf
[9] DDR4 SDRAM Standard, JEDEC JESD79-4, 2
Standard, 2012.
[10] LPDDR4 SDRAM Standard, JEDEC JESD209-4,
Standard, 2015.
[11] Graphics Double Data Rate (GDDR5) SGRAM
Standard, JEDEC Standard JESD212B.01,
2013.
[12] Y. Kim, V. Seshadri, D. Lee, J. Liu, and O.
Mutlu, "A case for exploiting subarray-level
parallelism (SALP) in DRAM," in Proc. ISCA,
2012.
[13] T. Kirihata, P. Parries, D. R. Hanson, H.
Kim, J. Golz, G. Fredeman, R. Rajeevakumar, J. Griesemer, N. Robson, A. Cestero, B. A. Khan, G. Wang, M. Wordeman,
and S. S. Iyer, "An 800-MHz embedded
DRAM with a concurrent refresh mode"
IEEE J. Solid-State Circuits, pp. 1377-
1387, 2005.
[14] C. J. Lee, V. Narasiman, O. Mutlu, and Y. N.
Patt, "Improving memory bank-level parallelism in the presence of prefetching," in
Proc. MICRO, 2009.
[15] D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, and O. Mutlu, "Tiered-latency
DRAM: A low latency and low cost DRAM
architecture," in Proc. HPCA, 2013.
[16] [Online]. Available: http://www.jedec.org/
mobiletaiwan2012

About the Authors
Chulwoo Kim (ckim@korea.ac.kr)
is a professor of electrical engineer-

IEEE SOLID-STATE CIRCUITS MAGAZINE

ing at Korea University, Seoul, where
he conducts research in the area of
analog and interface circuits. He is a
coauthor of two books: CMOS Digital Integrated Circuits: Analysis and
Design (McGraw Hill, fourth edition,
2014) and High-Bandwidth Memory
Interface (Springer, 2013). He served
on the Technical Program Committee
of the IEEE International Solid-State
Circuits Conference and as a guest
editor for IEEE Journal of Solid-State
Circuits. He is currently on the editorial board of IEEE Transactions on
VLSI Systems and is a Distinguished
Lecturer of the IEEE Solid-State Circuits Society for 2015-2016.
Hyun-Woo Lee is a coauthor of
High-Bandwidth Memory Interface
(Springer, 2013). He has authored
20 papers in the field of electronic
circuits and devices, nine of them
presented at the IEEE International
Solid-State
Circuits
Conference
(ISSCC). He holds more than 90 U.S.
patents. His total number of citations is over 500, including papers
and patents. He presented "LowPower Memory for Mobile I/O" in the
forum of ISSCC 2014. His current
focus includes high-speed and lowpower I/O design for DRAM, equalizers, DLL, PLL, and CDR. He worked
for SK Hynix, where he designed
and developed DDR2, DDR3, GDDR3,
GDDR5M, and GDDR5 products from
1997 to 2014.
Junyoung Song received the Ph.D.
degree in electrical and computer engineering from Korea University, Seoul,
in 2014. Since then, he has been with
the analog serial I/O team in the Programmable Solution Group at Intel,
where he is a senior design engineer.
He is also a coauthor of High-Bandwidth Memory Interface (Springer,
2013). He has authored over ten papers
in the field of wireline interface, four
of them presented at the IEEE International Solid-State Circuits Conference.
He received the Minister of the Ministry of Education's Science and Technology Award in the Korea Semiconductor
Design Contest (2011).
http://frankdenneman https://www.micron http://www.jedec.org/
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
