IEEE Solid-State Circuits Magazine - Spring 2016 - 36

Data Rate/Pin

10
LPSDR
LPDDR

GDDR6 (?)

LPDDR2
LPDDR3
LPDDR4

DDR1

LPDDR5 (?)

DDR2
DDR3
DDR4

DDR5 (?)

GDDR3
GDDR5

2000

2005

2007

2010

2013

2015

(Source: SK Hynix)
Figure 1: The bandwidth limitation of existing memory solutions.

Dynamic Random Access
Memory Technology
It is widely accepted in the processing and memory industries that the
performance of the main memory
system, namely dynamic random
access memory (DRAM), is critical
to unlocking the performance of the
next generation of high-performance
system architectures. In recent years,
the disparity in performance between
the processor and the external DRAM
subsystem is becoming more evident. This trend is fueled by the
explosion of high-performance applications such as graphics cards, data
center east-west workloads, missioncritical computing, as well as 100GbE
and beyond networking. Adding to
this mix is the projected growth of
the Internet of Things (IoT) and the

data generated by these interconnected smart devices or systems. IoT
will grow from 0.9 billion installed
units in 2009 to 26 billion units by
the year 2020 [1]. This growth will
outpace that seen in PCs and mobile
applications and will place a tremendous burden to scale the supporting
infrastructures.
Traditionally, the processor employs
multiple memory hierarchies such as
internal registers and cache memory to bridge the external memory
performance gap [2]. However, this
approach is reaching its logical limit
for next-generation processors. As
a case in point, in the 2000s era, the
area on a logic chip dedicated for onchip memory was roughly 30% of the
total logic area. Moving forward to
2017, it is anticipated on-chip memory

Table 1. The MaxiMuM bandwidTh derived froM CoMModiTy
draM SoluTionS.
ddr3 ×16
2,133 Mb/s

ddr4 ×16
3,200 Mb/s

Gddr5 ×32
7,000 Mb/s

Bandwidth per device

34 Gb/s

51 Gb/s

224 Gb/s

Power (normalized to mW/Gb/s/pin
of one piece of DDR3 × 16,2133, @
IDD4R)

1.0

0.96

0.58

4 Tb/s bandwidth implementation

120 devices

80 devices

18 devices

S P R I N G 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

will occupy up to 70% of the total logic
area in many processors. To unlock
the performance potential of next-generation, high-performance platforms,
the DRAM subsystem must overcome
three critical challenges.
The first challenge the DRAM
must overcome is bandwidth limitation from existing memory solutions.
Bandwidth is a product of input/
output (I/O) bus width and data rate
per I/O. From an I/O width perspective, current commodity double
data rate fourth-generation (DDR4)
devices are available in #4, #8 and
#16-b data bus widths, while lowpower (LP) DDR4 and graphics (G)
DDR5 solutions both offer 32-b wide
data bus. These I/O configurations
would provide sufficient bandwidth
for the current generation of processors had the data rate per I/O scaled
at the same rate with CMOS logic
technology. Since 2000, we have
seen a steady I/O data-rate improvement across the commodity DRAM
solutions as shown in Figure 1. As of
this writing, DDR4 is in mass production and specified to operate up to
3,200 Mb/s, while LPDDR4 is expected
to scale the I/O data rate to 4,266 Mb/s.
Furthermore, GDDR5 devices are available at over 7,000 Mb/s I/O data rate.
The total maximum bandwidth realized with these solutions are shown
in Table 1. We anticipate next-generation network and computing processors would require on average 4 Tbs−1
bandwidth from the DRAM subsystem.
To deliver the required bandwidth,
an implementation with DDR4 #16 at
3,200 Mbs−1 would require 80 devices,
30 devices with LPDDR4, and 18 devices
with GDDR5.
In certain high-performance computing applications, it is not uncommon to see 8 Tbs−1 bandwidth
required from the DRAM subsystem.
Achieving 8 Tbs−1 with on-die memories will place a tremendous impact
on the processor package size or the
system printed circuit board (PCB)
area required by external DRAM
components or modules. Therefore,
a small form factor is the second
challenge the DRAM subsystem must

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016