IEEE Solid-State Circuits Magazine - Spring 2016 - 37

Through Silicon Via Technology
Enables 3D DRAM ICs
The key driving forces behind TSV
development across the IC industry,
whether in memory, field-programmable gate array (FPGA), or CMOS
logic plus memory, are performance
and form factor. In memory ICs, gate
delay time at the 22-nm technology
node is lower than 0.5 p/s, while
the circuit wire delay time can be
near 2,000 p/s [4]. The TSV packaging process involves three major
steps: TSV formation, planar thinning of the layer(s), and alignment
and bonding [5]. Currently, deepreactive ion etching technology,
or the Bosch process, is the most
common method for the formation

100%

Normalized DDR256 = 100%

address in next-generation, high-performance systems. The system PCB
or chip package size is fixed or restricted in many systems, whether in
the networking line card or the server.
Allocating more PCB or chip package
space to the memory is a significant
architectural issue. Furthermore, an
implementation using external DRAM
devices will require more power to
drive the external traces.
The third challenge the DRAM
system needs to address is power
efficiency. It is not a secret that
reducing power and increasing performance is always a tradeoff. Commodity DRAM has come a long way
in terms of power efficiency. Figure 2
shows the power efficiency of DDR
to DDR4, normalized to a DDR1 256 Mb.
Each subsequent generation of commodity DRAM provides a significant
power savings over the previous one.
The current DDR4 devices exhibit
over 90% normalized power efficiency when compared to DDR1.
However, the trend of power efficiency improvement is tapering off.
Therefore, the DRAM technology must
seek novel methods to improve overall power efficiency. Within the memory industry and specifically DRAM
solutions, through silicon via (TSV)
technology is providing the path to
scale power efficiency, bandwidth
and form factor.

Power Efficiency

DDR 256 Mb

DDR
Gb/s

80%

0.4

DDR2 DDR3 DDR4
0.8

1.6

3.2

-57%

60%
DDR2 1 Gb
40%

20%

-79%

DDR3 4 Gb

2002 2003
(Source: SK Hynix)

2012 2014

Figure 2: The power efficiency of commodity draM technologies.

of TSVs with diameters from 100 to
10 μm. The Bosch process involves
alternating cycles of silicon isotropic etching and wall passivation.
The etching product, SiFx, is formed
when SF6 or NF3 are introduced in
an Ar environment. Wall passivation
is accomplished by C4F8 in Ar to

tapered via that can offer a higher
aspect ratio [8]. TSVs with higher
aspect ratios have a higher propensity to have scalloping at the regions
near the top of the TSV wall due to
the wider paths of the radical ions.
At the bottom of the via, the paths
that radicals travel are more focused

In recent years, the disparity in performance
between the processor and the external DRAM
subsystem is becoming more evident.
form a polymer deposition on the
sidewalls and bottom of the via.
Today, an advanced etching process
can yield TSVs with diameters in the
few microns [6]. TSVs typically have
aspect ratios between one and ten,
although methods for achieving a
very high aspect ratio greater than
20 have been demonstrated [7]. A
phenomenon that occurs with etching is that the via depth has been
shown to decrease as a function of
etching time [8]. The etching duration will also impact the profile of
the TSV. The TSV has two profile
variants: a straight-walled via or a

and scalloping is less common. Scalloping effects can be reduced by
controlling the etch rate and TSV
diameters. Advanced gas switching
systems with actuation times below
20 ms greatly improve the ramping
and switching rate [9] leading to the
reduction of scalloping. It has been
shown that scalloping can be reduced
from 0.2 μm to 40 nm [5].
Once the TSVs have been formed,
the starting point of 3D IC stacking
begins with the device wafer front
bumped and singulated. Next, the
devices (dice) are placed and bonded
on a carrier wafer. Temporary carrier

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016