IEEE Solid-State Circuits Magazine - Spring 2016 - 38

Side Molding

DRAM Slice
DRAM Slice
DRAM Slice

SoC

DRAM Slice
DA Ball

TSV

PHY

Interposer

Figure 3: The 2.5d integration and hbM illustrating hbM base and top dice.

wafers are required for handling
the thinned wafers in the subsequent
steps. The devices on the carrier
wafer would then need to be ground
to achieve the desired thickness. Thinning of the dice is required in ICs utilizing TSVs due to the limitation of the
maximum TSV depth, which can be
economically created. Dice thinning

the stack; i.e., not the base die wafer,
the carrier wafer is debonded from
the dice after stacking.
From a DRAM memory perspective,
TSV, an interchip connection technology, makes it possible to increase the
memory capacity, reduce package
dimensions, and leads to improved
power efficiency. Increasing memory

The key driving forces behind TSV development
across the IC industry, whether in memory,
field-programmable gate array, or CMOS logic
plus memory, are performance and form factor.
is also needed to achieve the desired
z-thickness of the final stacked
package and to limit parasitic signals. Today, with coarse and fine
grinding processes, silicon wafers
could be ground to as low as 50 μm
[9]. Thinning of the silicon wafer is
delicate due to an exponential correlation between wafer strength and
thickness. It has been shown that a
7% reduction of the original wafer
thickness results in a 60% reduction
in breaking strength [5]. Breaking
strength is the perpendicular force
required to cause the chip to crack.
Once the desired thickness of the
device wafer is reached and the TSV
revealed, the back sides of the dice
are bumped for stacking additional
dice. In subsequent layers of dice in

S P R I N G 2 0 16

density has always been one of the
key objectives for the DRAM industry. TSVs allow vertically stacked
DRAM dice to be connected, thereby,
increasing memory density for a
given area. It is theoretically possible to use TSVs as interconnections
for upwards of 16 DRAM dice stack.
Stacking a higher number of dice
may lead to DRAM refresh timing
issue for the upper dice. DRAM dice
using TSV as interconnections, such
as the HBM DRAM dice, will need to
be thinned during the stacking process to meet the height of the processor die, as previously discussed. In
a stack with 12 or more DRAM dice,
the dice will need to be thinned further, which can lead to reduced body
strength leading to cracking. Modern

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TSV technologies with 10-35-μm
pitch allows for hundreds of TSVs as
interconnections between the DRAM
dice in a 3D stack leading to smaller
package. Reducing the overall package dimensions leads to better signal
integrity due to shorter interconnection lengths, resulting in a higher
data transfer rate. Compared to conventional DRAM packages that use
long wire bonds to connect the DRAM
to the I/Os, the shorter traces of
TSV exhibit lower capacitance leading to reduced energy consumption
required for the transfer of data.
The HBM device is a 3D-stacked
DRAM leveraging TSV to increase bandwidth, improved power efficiency, and
form factor. Currently, HBM is available
in several stack options: two-, four-,
and eight-dice high. Figure 3 shows a
four-dice high HBM on a HBM base die.
In layers 0-3, the top metal line of each
layer is connected to the microbump
of the DRAM layer above, while the
bottom metal line is connected to the
TSV. Layer 4 in this illustration, or the
top die of the HBM, would not require
TSVs and can be background to varied
z-thickness, depending on the applications and the assembly process.

High Bandwidth Memory
Based on TSV Technology
The HBM, a JEDEC standard memory
device, incorporates a TSV to enable
3D stacking of DRAM dice and wideinterface architecture to achieve the
bandwidth, power efficiency, and

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016