IEEE Solid-State Circuits Magazine - Spring 2016 - 39
(a)
(b)
Item
(a)
(b)
Bump
Value
Gen1-Package Dimension (X, Y )
5.48 mm × 7.29 mm
Gen2-Package Dimension (X, Y )
7.75 mm × 11.87 mm
Gen2-Package Body Height (Z )
0.49 mm
Gen2-Package Body Height (Z )
0.72 mm
CD
Pitch
25 µm
(As Reflow)
55 µm
-
-
JEDEC
Micro Bump Array (MPGA)
Remark
JC11-2.883, JC11-4.884
Side Mold
Base Die
Micro Bumps
Silicon
Side Mold
(Source: SK Hynix)
Figure 4: The SK hynix hbM packaging dimension.
form factor required by the nextgeneration system architecture.
Figure 4 illustrates the packaging
structure from SK Hynix, and Figure 5
shows the architecture of the HBM
device. The HBM memory consists
of multiple DRAM stacks, with
each DRAM stack supporting up to
eight channels. Current solutions
offered by DRAM vendors include
two-, four-, and eight-high stacks of
DRAM dice; each additional die provides additional capacity to the HBM
device. JEDEC specification allows
DRAM vendors to have the option to
include a base layer at the bottom of
the HBM stack for signal redistribution and other DRAM vendor specific functions.
Currently, HBM available in the
industry comes with the base layer.
High-bandwidth operation is realized by the wide interface aggregated
from each independent channel
within each DRAM stack. Each channel provides 128 I/Os so that a HBM
solution with eight channels will provide 1,024 I/O. Due to the wide interface, the HBM achieves low power
and high energy efficiency per pin
by implementing a low I/O data
rate. A HBM solution that operates
at 1.0 Gb/s per pin and 1,024 I/O
will deliver 1 Tb/s bandwidth. SK
Hynix anticipated this solution to
provide a power reduction of over
60% when compared to a GDDR5
implementation, as shown in Figure 6.
SK Hynix also illustrated that this
CH-7
CH-5
CH-3
CH-6
CH-4
CH-2
CH-0
CH-1
PS-CH0
PS-CH1
PS-CH0
PS-CH1
B0~3
B0~3
B0~3
B0~3
B4~7
B4~7
B4~7
B4~7
64 I/O
ADD
CMD
64 I/O
64 I/O
ADD
CMD
64 I/O
B8~11
B8~11
B8~11
B8~11
B12~15
B12~15
B12~15
B12~15
8 Gb Core Die
(Source: SK Hynix)
Figure 5: an example architecture of the JedeC implementation of hbM.
IEEE SOLID-STATE CIRCUITS MAGAZINE
S P R I N G 2 0 16
39
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
IEEE Solid-State Circuits Magazine - Spring 2016 - Cover1
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IEEE Solid-State Circuits Magazine - Spring 2016 - 1
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IEEE Solid-State Circuits Magazine - Spring 2016 - Cover3
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