IEEE Solid-State Circuits Magazine - Spring 2016 - 4

editor's note

R. Jacob Baker

Welcome to the Spring 2016 Issue
of IEEE Solid-State Circuits Magazine!

This issue of IEEE Solid-State Circuits
Magazine is an overview of semiconductor memory including emerging
memory technologies, packaging, interfaces, memory applications, and
dynamic and nonvolatile memory technologies. Guest Editor Dr. Tim Hollis
has pulled together industry/academic
experts and colleagues from around
the world to write articles discussing current and future semiconductor
memory technologies, implementations,
and uses.
Over several decades, the scaling of computing performance has
always been a strong function of the
associated memory technologies. To
support the insatiable demand for
system performance, memory has
scaled in capacity (bits), speed (bitsaccessed/time), and, more recently,
function (nonvolatility, etc.). In this
issue, several experts provide their
insights into all aspects of semiconductor memory evolution, from the
distant past on into the future.
The issue begins with "The History of Semiconductor Memory," as
recounted by Dean Klein, Micron
vice president of Advanced Memory
Solutions. He takes us back to a time
predating the emergence of semiconductor memories and then walks
us along the path of memory technology evolution. He reminds us of
the wildly changing make-up of the
memory industry over the years and
provides a sneak peak into some of

Digital Object Identifier 10.1109/MSSC.2016.2548431
Date of publication: 21 June 2016

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the more revolutionary opportunities yet to come.
In the second article, "Memory
Interfaces," Dr. Chulwoo Kim, professor of electrical engineering at Korea
University, highlights many of the
key innovations that have enabled
the ever-increasing speeds of memory access over the last two and a
half decades. Dr. Kim also looks forward, anticipating architectural and
circuit-based enhancements that will
enable memory bandwidth scaling
to continue into the future.
In the third article, "Scaling the
Next-Generation System Architecture,"
Kevin Tran, senior manager of Technical Marketing for SK Hynix, focuses
on more recent memory architectures
enabled through vertical integration and how 2.5D and 3D integration can be exploited to extend
both memory speed and capacity
going forward.
At the most fundamental level,
memory-cell engineering has been
the heart of consistent progress in
memory performance, whether it be
through scaling a particular technology to smaller and smaller nodes
through materials and device engineering and advancing lithography
tools and techniques or the introduction of completely new storage
mechanisms (e.g., NAND flash in
the 1980s). In the background of
the often-chaotic memory industry
has been the ongoing search for
new storage recipes. In his article,
"Emerging Memory Technologies,"
Dr. Shimeng Yu, assistant professor of
electrical and computer engineering

IEEE SOLID-STATE CIRCUITS MAGAZINE

Guest Editor Dr. Tim Hollis.

at Arizona State University, provides
a broad survey of those technologies competing for future adoption,
including the underlying storage
mechanisms of each, as well as how
the idosyncracies of each technology
make them suitable or otherwise for
memory applications as we understand them today.
Thanks to the laws of physics, traditional memory scaling is becoming
more and more complicated and less
and less economical with each new
node. While monolithic and stackingbased integration provide relief, there
are other opportunities to advance
system performance through memory. In his article, "Making the Case
for Feature-Rich Memory Systems,"
Dr. Rajeev Balasubramonian, professor with the University of Utah's
School of Computing, explains how
smarter memory technologies, by
offloading a portion of the compute
burden from the processor through
simple, fundamental operations, can
(continued on p. 112)

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016