IEEE Solid-State Circuits Magazine - Spring 2016 - 40

Power Consumption at 128 Gb/s
12.0
GDDR5 7.0 Gb/s (×32)

DDR4 2.0 Gb/s (×16)

DDR3 2.0 Gb/s (×16)

HBM1 1.0 Gb/s (×1 K)

8.4
8.0
(Watt)

6.4
-60%
4.48
4.0

HBM1

3.3

0.0
(Source: SK Hynix)
Figure 6: a power consumption comparison of commodity draM versus hbM.

1 Tb/s implementation with HBM is
37 times smaller in size when compared to a DDR4 implementation
used to achieve the same bandwidth.
There are two methods to integrate 3D-stacked DRAM, like the
HBM, to the processor die. The first
method is to attach the HBM directly
onto the processor. This method is
commonly known as 3DS integration
and would not require the use of
interposers. 3DS integration is suitable for processors with low power
consumptions as thermal dissipation
can become challenging for processors with higher power. Today's processors, such as network processing
units (NPUs), graphics, and those
used in high-performance computing, can have power consumption
beyond 100 W and would require
thermal dissipation solutions. The
3DS integration of these processors with HBM can lead to excessive
DRAM cell leakage due to the high
thermal dissipation from the processor directly to the HBM. The HBM
refresh rate could be adjusted to
compensate for the elevated DRAM
cell leakage. However, as mentioned
previously, in many applications,
the power signature and thermal
dissipation of the processor make it

S P R I N G 2 0 16

unfeasible to directly stack the HBM
onto the processor die. Figure 7 [4]
illustrates the thermal performance
challenge anticipated in a true 3DS
integration of logic die and memory
die [4]. For processors using thermal
dissipation solutions like heat sinks,
in a 3DS integration, the heat must
dissipate from the processor to the
HBM stack and then to the heat sink.
This package configuration can lead
to thermal trapping at the processor. The second and more imminent
method is to utilize an interposer to
connect the HBM in a side-by-side
configuration to the processor die.
This method is commonly known
as 2.5D integration. The interposer,
whether silicon or fine pitch organic,
facilitates the connection between
the HBM and the processor via
fine pitch metal lines. Today, most
interposers designed for 2.5D integration of HBM range from four to
six metal layers.

2.5D Integration Activities
in the Industry
The heterogeneous integration of IC
devices on the same interposer and
packaged as one system-in-package
(SiP) is enabled by 2.5D. The SiP is able to
integrate CMOS logic die, RF devices,

IEEE SOLID-STATE CIRCUITS MAGAZINE

and memory devices, to name a few,
in different process technologies.
The 2.5D SiP can achieve an improvement of 100 times in interdie bandwidth per watt and up to 50% power
savings. Contrary to common misconceptions, 2.5D integration results
in a lower cost of the final package.
Xilinx's Virtex 7-200T was among the
first commercialized devices based
on 2.5D integration. The device features 2 million logic cells supported
by four FPGA subdice integrated on
a four metal layer 65-nm process
node silicon interposer with TSV
[10]. The Virtex 7 silicon interposer
is passive and does not contain any
transistors, therefore having fewer
risks and no TSV-induced performance degradation [10]. By integrating four smaller FPGA die into
a 2.5D package, the Virtex 7 exhibits better capacity, bandwidth, and
power when compared to an implementation with four discrete FPGA
devices. The Virtex 7-200T features
19 W of total power versus 112 W
for a discrete FPGA implementation;
20 W per FPGA and 8 W per chip-tochip interface [10]. The cost of the
Virtex 7-2000T is lower when compared to a monolithic implementation. When relative cost, taking
into account silicon yield, package
laminate, and assembly, is normalized to a large monolithic FPGA
silicon die (die cost ~ 0.9, laminate
cost ~ 0.05, assembly cost ~ 0.02),
the 2.5D implementation with four
smaller FPGA dice shows an almost
50% lower total cost (die cost ~ 0.24,
silicon interposer cost ~ 0.1, laminate cost 0.05, assembly cost ~ 0.4)
[11]. The die cost reduction is markedly lower due to an improved yield
with smaller FPGA die versus a large
monolithic die. Furthermore, the
silicon interposer cost is an incremental cost in 2.5D integration as
it is distributed to additional die in
the package [11]. The cost reduction
is also seen in NPUs with 2.5D memory integration. When comparing an
NPU with 110 Mb of 6T SRAM on a
die to a 2.5D implementation of the
same NPU with 2 Gb DRAM, the total

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