IEEE Solid-State Circuits Magazine - Spring 2016 - 41

Baseline Case-θJA Model, Still Air, Ambient = 50 °C
(13-mm Lid Size, 0.2-mm Lid Thickness, TIM = 3 W/m-K, Burst ON, P = 6.91 W)

H/S
Memory
Logic

Temperature (°C)
176.010
170.867
165.724
160.581
155.439
150.296
145.153
140.010
134.867
Logic Hot Spot at O-3 and O-4, T = 176 °C

Package Structure

Temperature (°C)
166.201
163.903
161.605
159.306
157.008
154.710
152.411
150.113
147.815
Memory Hot Spot T = 166.2 °C

Velocity (m/s)
0.147592
0.129143
0.110694
0.0922450
0.0737960
0.0553470
0.0368980

Logic Die Tmax = 176 °C
Memory Die Tmax = 166.2 °C
Lid Top Tmax = 160.2 °C
Lid Top Tcenter = 155.4 °C
θJA = 18.23 °C/W
ψJT = 2.98 °C/W

0.0184490
0.000000
Source: Amkor [4], Presented by C Lee at the 2013 SiP Global Summit.
Figure 7: The thermal performance challenge in the 3dS integration of a logic die with a memory die [3].

cost for the 2.5D implementation is
about 17% lower [11]. The large die
size of the NPU with 110 Mb of SRAM
causes significant yield impact and
is projected to be 60% of the total
cost of the original NPU [11]. Utilizing 2.5D integration of the NPU with
2Gb DRAM leads to a 75% reduction
in the NPU die cost [11].
A key topic in 2.5D IC integration is the readiness of various
interposer technologies. Currently,
silicon interposer is the prevalent choice for 2.5D integration of
devices like the HBM where the
ubump pitch is tight. JEDEC defined
the HBM with base die ubump pitch
at 55 μm. Silicon interposer shipping today can be at a legacy process
node. For example, the Xilinx Virtex
7 silicon interposer is at 65-nm process node [10]. Silicon allows the
densest routing with interconnect
dimensions at 1-μm line, space, and
thickness. In 2.5D integration, the
larger the silicon interposer size,
the more devices can be integrated

on the interposer, thereby, improving overall performance. TSMC has
demonstrated full reticle size capability of 26 nm # 32 nm and, for
applications requiring larger reticle
size, has a project which evaluated
capability to support 1.5# the reticle
size, with interposer size of 26 mm #
48 mm [12].
Organic interposer is an attractive
alternative to silicon. Today, organic
interposers are capable of finer design
rules than conventional substrate
materials. Line and space dimensions
can reach 5-6 μm design rules. The
industry anticipates organic interposer technologies to address the
silicon interposer size limitation and
potentially yield as much as a 50%
cost reduction over silicon. Organic
interposers also address the warpage issue potentially seen with silicon interposer. Due to the coefficient
of thermal expansion mismatched
between a silicon interposer and an
organic substrate used in IC packaging, warpage is a known issue in

silicon interposer implementations
[13]. Organic interposers exhibit less
high temperature warpage due to the
symmetric structure [4].

Quality/Reliability Post 2.5D
Assembly with HBM
A key topic with HBM and 2.5D integration is ensuring the integrity of
the HBM device post 2.5D assembly. The HBM device offers DRAM
cell repair and interconnect remapping to improve SiP assembly yield.
The native memory built-in-self-test
(MBIST) engine on the HBM base
die allows DRAM cells to be tested
and repaired after the SiP assembly
process via the IEEE 1500 interface.
The MBIST, upon locating a DRAM
cell fault, will provide a location
or address of the fault. Soft repair
can be performed to ensure that
the DRAM fault is repairable. Once
confirmed by MBIST that the original fault no longer occurs, hard
repair can be performed using one
of the available redundant rows for

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016