IEEE Solid-State Circuits Magazine - Spring 2016 - 42

SoC

HBM PAD

HBM Internal

SoC

HBM PAD

HBM Internal

DBI

DBI

DBI

DQ7

DBI

DBI Not U

DQ7

DQ7

DQ7

DQ6

DQ7

DQ7

DQ6

DQ6

DQ6

DQ5

DQ6

DQ5

Hi-Z

sed

DQ4

DQ4

DQ4

DQ4

DQ6
d
DQ5
ske
Ma
DQ4

DQ3

DQ3

DQ3

DQ3

DQ3

DQ3

DQ2

DQ2

DQ2

DQ2

DQ2

DQ2

DQ1

DQ1

DQ1

DQ1

DQ1

DQ1

DQ0

DQ0

DQ0

DQ0

DQ0

DQ0

DM

DM

DM

DM

DM

DM

DQ5

DQ5

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Figure 8: an interconnect repair via ubump remapping.

permanent repairing the fault. Since
there's limited redundant rows on
the HBM device, soft repair acts as
a means to ensure that redundant
rows are efficiently utilized. Faults
related to interconnection ubumps
on the base die can also be detected
and repair via the EXTEST, MISR, and
LSFR functions. Figure 8 illustrates
the interconnection ubump remapping mechanism. Once an interconnect ubump is located, reserved
interconnections can be used to
remap failed command and address
and the DBI pin can be used to remap
failed data I/O interconnections.

Conclusion
TSV is enabling a new group of
3D memory ICs such as the HBM
device to deliver the performance
and power efficiency in an optimized package, which is opening
new paths for next-generation system architectures. Today, the HBM
device delivers an unprecedented
bandwidth of up to 2 Tbs−1, and
DRAM vendors are looking into doubling this bandwidth in the nextgeneration HBM. SiPs utilizing 2.5D
integration of HBM and processor
die have been in mass production,
proving the feasibility of integrating TSV-based 3D IC memory and
the 2.5D integration flow. As of this
writing, silicon is the interposer of

42

S P R I N G 2 0 16

choice for 2.5D programs. Organic
interposers promise to scale the
reticle size limitation of silicon and
are expected to be commercialized
in the next few years. As more TSVbased products enter mass production, the TSV technology will be
improved to enable an even higher
number of stacked dice and memory
subsystem performance.

References

[1] Gartner. (2013). Forecast the internet
of things, Worldwide 2013. [Online].
Available: http://www.gartner.com/do
cument/2625419?ref=QuickSearch&sth
kw=G00259115
[2] B. Jacob, S. W. Ng, and D. T. Wang, Memory
Systems Cache, DRAM, Disk. San Mateo,
CA: Morgan Kaufmann, 2008.
[3] R Huemoeller, "TSV market drivers,
demand and product readiness," in
Proc. The ConFab, 2012, p. 4.
[4] C. Lee, "From advanced package to
2.5D/3D IC," in Proc. SiP Global Summit,
2013, p. 17.
[5] P. Garrou, C. Bower, and P. Ramm, Eds., "Introduction to 3D integration," in Handbook
of 3D Integration, vols. 1 and 2. Hoboken,
NJ: Wiley, 2012, pp. 1, 79, 184, 187.
[6] M. Koyanagi, T. Fukushima, and T. Tanaka, "High-density through silicon vias
for 3D LSIs," Proc. IEEE, vol. 97, no. 1, pp.
49-59, Jan. 2009.
[7] A. C. Fisher, S. J. Bleiker, T. Haraldsson, N.
Roxhed, and G. Stemme, "Very high aspect
ratio through-silicon vias (TSVs) fabricated
using automated magnetic assembly of
nickel wires," J. Micromech. Microeng., vol.
22, no. 10, pp. 37-40, Oct. 2012.
[8] L. Cunnane, A. Kiermasz, and G. Ditmer,
Characterization of TSV Processes Utilising Mass Metrology. Bristol, UK: Metryx,
2009.
[9] S. E. Schulz, "3D integration, TSV processes and wafer thinning." Fraunhofer
Institute for Electronic Nanosystems.

IEEE SOLID-STATE CIRCUITS MAGAZINE

[10] I. Bolsens. (2011). 2.5D ICs: Just a stepping
stone or a long term alternative to 3D?
[Online]. Available: www.xilinx.com
[11] P. Marcoux, "2.5D and 3D TSV products," in Proc. IEEE SCV Chapter, Components, Packaging and Manufacturing
Technology Soc., May 2011, pp. 000434-
000457.
[12] J. Tzou, on behalf of TSMC. "TSMC demonstrates readiness for 3D-IC," presented
at the GSA Memory+ Conf., 2013. [Online]. Available: www.techdesignforums.
com
[13] K. Murayama, M. Aizawa, K. Hara, M.
Sunohara, K. Miyairi, K. Mori, J. Charbonnier, M. Assous, J. P. Bally, G. Simon,
and M. Higashi, "Warpage control of
silicon interposer for 2.5D package application," in Proc. 63rd IEEE Electronics
Components and Technology Conf., 2013,
pp. 879-884.

About the Author
Kevin Tran (kevin.tran@us.skhynix.
com) is a senior manager of technical
marketing at SK Hynix, where his primary focus is on memory solutions
for high-performance applications
including networking, high-performance computing, and ARM server
class systems-on-a-chip. He is also
the HBM program manager for SK
Hynix America and has been developing the ecosystem to enable HBM and
2.5D integration since 2011. He has
more than 14 years of experience in
applications engineering and technical marketing in the semiconductor
industry and has worked for Atmel,
Micron, and Nanya before joining
SK Hynix.
http://www.xilinx.com http://www.techdesignforums http://www.gartner.com/do
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