IEEE Solid-State Circuits Magazine - Spring 2016 - 44
for nonvolatile processor, and synaptic
device for neuro-inspired computing.
states can be triggered by an electrical stimulus (i.e., voltage or current pulse). However, the detailed
switching physics is quite different: STT-MRAM relies on the parallel configuration (corresponding to
LRS) and antiparallel configuration
(corresponding to HRS) of two ferromagnetic layers separated by a thin
tunneling insulator layer; PCRAM
relies on chalcogenide materials
to switch between the crystalline
phase (corresponding to LRS) and
the amorphous phase (corresponding to HRS); and RRAM relies on the
formation (corresponding to LRS)
and the rupture (corresponding to
HRS) of conductive filaments in the
insulator between two electrodes.
Table 1 compares the typical device
characteristics of the emerging
memory technologies and the mainstream memory technologies.
Due to the different underlying
physics, the device characteristics
are also different among emerging
NVMs. Therefore, different emerging
NVMs may have different application
spaces due to their unique characteristics. As compared to SRAM, STTMRAM has an advantage of a smaller
cell area, while STT-MRAM has maintained low programming voltage, fast
write/read speed, and long endurance. Thus, STT-MRAM is attractive as a replacement for embedded
degradation of performance, reliability, and noise margin. In this context,
emerging memory technologies that
are noncharge based are actively
under research and development in
the industry, with the hope of revolutionizing the memory hierarchy [1].
The ideal characteristics for a
memory device include fast write/
read speed (10 years), long write/read
cycling endurance (>1017 cycles), and
excellent scalability (<10 nm). Nevertheless, it is almost impossible to satisfy all of these ideal characteristics
in a single "universal" memory device.
Several resistance-based emerging
NVM technologies have been pursued
toward achieving part of these ideal
characteristics. The emerging NVM
candidates include STT-MRAM [2],
PCRAM [3], and RRAM [4].
These emerging NVM technologies share some common features:
they are nonvolatile two-terminal
devices, and they differentiate their
states by the switching between a
high resistance state (HRS, or off
state) and a low resistance state
(LRS, or on state). The switching
from off state to on state is called
"set," and the switching from on
state to off state is called "reset."
The transition between the two
Overview of Emerging Memory
Technologies
The functionality and performance
of today's computing system are
increasingly dependent on the characteristics of the memory subsystem. The memory subsystem has
a well-known memory hierarchy:
Today static random-access memory (SRAM), dynamic random-access
memory (DRAM), and flash are the
mainstream memory technologies
serving as cache, main memory, and
storage memory such as solid-state
drive (SSD), respectively. Moving
up the memory hierarchy toward
the cache, the memory write/read
latency decreases. Moving down the
memory hierarchy toward the storage, the memory capacity increases.
These mainstream memory technologies are essentially based on the
charge storage mechanism: SRAM
stores the charges at the storage
nodes of the cross-coupled inverters, DRAM stores the charges at the
cell capacitor, and flash stores the
charges at the floating gate of the
transistor. All these charge-based
memories face challenges in scaling down to the 10-nm node and
beyond. The easy loss of the stored
charges at nanoscale results in the
Table 1. Device characTerisTics of mainsTream anD emerging memory Technologies.
mainsTream memories
emerging memories
flash
sram
Dram
2
nor
2
nanD
2
sTT-mram
2
Pcram
2
rram
Cell area
>100 F
6F
10 F
<4F (3D)
6~50F
4~30F
4~12F2
Multibit
1
1
2
3
1
2
2
Voltage
<1 V
<1 V
>10 V
>10 V
<1.5 V
<3 V
<3 V
Read time
~1 ns
~10 ns
~50 ns
~10 µs
<10 ns
<10 ns
<10 ns
Write time
~1 ns
~10 ns
10 µs-1 ms
100 µs-1 ms
<10 ns
~50 ns
<10 ns
Retention
N/A
~64 ms
>10 y
>10 y
>10 y
>10 y
>10 y
Endurance
>1E16
>1E16
>1E5
>1E4
>1E15
>1E9
>1E6~1E12
Write energy (J/bit)
~fJ
~10fJ
~100pJ
~10fJ
~0.1pJ
~10pJ
~0.1 pJ
2
Notes: F: feature size of the lithography. The energy estimation is on the cell-level (not on the array-level). PCRAM and RRAM can achieve less than
4F2 through 3D integration. The numbers of this table are representative (not the best or the worst cases).
44
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