IEEE Solid-State Circuits Magazine - Spring 2016 - 46
the perpendicular MTJ achieves the
shape anisotropy in the vertical
dimension, allowing better scalability in the lateral dimension. State-ofthe-art perpendicular MTJ cells have
been scaled to 15 nm [11], [12].
Today STT-MRAM's process and
manufacturing technology are relatively mature. However, STT-MRAM
has relatively poor process compatibility with mainstream silicon CMOS
or RRAM counterparts. The current
trend of PCRAM cell design is to
switch from the mushroom cell
[Figure 1(c)] to the pillar cell [Figure 1(d)] to confine the heat dissipation, thereby reducing the
write current. An extremely scaled
PCRAM cell using the carbon-tube
electrodes suggests that the write
current can achieve ~1 μA at 2-nm
node [16]. The PCRAM's switching
The functionality and performance of today's
computing system are increasingly dependent
on the characteristics of the memory subsystem.
technology, because more than ten layers of exotic ferromagnetic materials
(typically CoFeB/MgO) are used in the
MTJ stack. In addition, keeping within
the thermal budget to crystallize all
the magnetic layers while maintaining downward CMOS doping profiles
is challenging. The precise deposition
and etching to avoid the formation
of dead layers/regions of the complicated MTJ stack add another significant cost barrier for foundries to
widely adopt this technology.
PCRAM Cells
The PCRAM cells are typically based
on GST materials (e.g., Ge2Sb2Te5).
The GST material systems can further be tuned for device characteristics that are of interest. For
example, Ge-rich GST (N-doped)
could be used to achieve better
data retention for high temperature automotive applications [13].
The PCRAM's on/off resistance
ratio is much larger (in the range
of 100-1,000×) than STT-MRAM.
Thus, in principle, multilevel cell
(MLC) operations are allowed (even
4 b/cell are feasible [14]). The key
challenge for PCRAM cell design is
the relatively large write current
required to melt the phase-change
materials. Even for state-of-the-art
PCRAM at 20 nm, the write current
(~100 μA [15]) is roughly three to
ten times larger than its STT-MRAM
46
S P R I N G 2 0 16
speed (>50 ns) is limited by the
slow crystalline process, also ten
times longer than its RRAM counterparts, while the PCRAM's endurance
(10 6 +10 9 cycles) is comparable to
that of the RRAM. The PCRAM's data
retention (especially for the MLC)
is limited by resistance drift due
to the relaxation of the amorphous
state. Thus, sophisticated circuitlevel compensation schemes are
needed [17]. Despite the fact that the
PCRAM's cell characteristics are less
competitive than RRAM in terms of
the write power and speed, today
PCRAM's process and manufacturing technology is quite mature.
PCRAM has generally good process
compatibility with mainstream silicon CMOS technology, as GST materials can be deposited by sputtering
under back-end-of-line (BEOL) temperature (<400 oC).
RRAM Cells
There are two subcategories within
RRAM: oxide-RAM (OxRAM) and conductive bridge RAM (CBRAM). The difference is that OxRAM's filament consists
of oxygen vacancies in the oxide layer
[Figure 1(e)], while CBRAM's filament
consists of metal atoms, formed by
fast-diffusive Ag or Cu ions migrating
into the solid-electrolyte [Figure 1(f)].
Despite different underlying physics,
these two types of RRAMs share many
common device characteristics. The
IEEE SOLID-STATE CIRCUITS MAGAZINE
only notable difference may be that
OxRAM's on/off resistance ratio may
be smaller (in the range of 10-100×)
and offers better endurance up to
1012 cycles, while CBRAM's on/off
resistance ratio can be quite large
(103-106×) but with limited endurance
(<104 cycles) [18]. The switching of
RRAM includes unipolar and bipolar
modes depending on the oxide and
electrode materials system [19]. The
unipolar mode generally requires
larger write current and shows less
endurance; thus, the bipolar mode
is preferred. The key challenge of
RRAM cell design is the variability of
the switching parameters. Owing to
the stochastic nature of ionic (oxygen
vacancies or metal ions) migration,
the filament shape varies from device
to device and also from cycle to cycle
(within one device). Remarkable variation in resistance distribution (which
can be one or two orders of magnitude) adds challenges to the sensing
circuit design and requires the writeverify techniques to program to the
target states, which could be latency
consuming for the MLC operations.
Although RRAM could require smaller
write current (e.g., ~10 μA) due to the
filamentary switching mechanism,
the data retention may be problematic
when filament is too thin [20], and at
the same time the random telegraph
noise due to the filament instability
may become significant [21]. Nevertheless, the scalability to 2-nm node
of RRAM cell has been demonstrated
by sidewall electrodes [22]. RRAM has
generally excellent process compatibility with the mainstream silicon
CMOS technology, as many RRAM
materials (e.g., HfOx, TaOx) are already
used in silicon transistors' high-k
dielectric process. Atomic-layer deposition allows for the accurate deposition of RRAM thin film under BEOL
temperature (<400 oC).
Emerging NVM Array Architectures
and Circuit-Level Design Challenges
1T1R Array Architecture
One of the common emerging NVM
array architectures is the 1T1R array.
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