IEEE Solid-State Circuits Magazine - Spring 2016 - 48

Selected Cell

Selected Cell
WL

1V
2 W

1V
3 W

1V
2 W

1V
3 W

Selector
1V
2 W

1V
2 W
(a)

Selected Cells

2V
3 W

VR
VR

Write Power (W) Access Vw(%)

100
80
60
40
20
0
10 m

Nonlinearity
Linear
10x
100x
1,000x

100 µ

2V
3 W
(b)

(c)

128 256 512 1,024
Array Size (N × N)
(d)

Figure 3: a schematic of the cross-point array. The selector is added in series with
the rram cell at each cross-point. (a) v/2 write scheme. (b) v/3 write scheme. (c) read
scheme (for an entire row). (d) sPice simulation of write margin and write power as a
function of cross-point array size. increasing the nvm cell's i-v nonlinearity (N) by adding
selectors is helpful to minimize the ir drop problem along the interconnect wire and the
sneak path problem.

rows and columns perpendicular
to each other with NVM cells sandwiched in between, as shown in
Figure 3(a). The cross-point array,
in principle, can achieve a 4 F2 cell
area; thus, it can achieve higher
integration density than the 1T1R
array. Typically, the selectors are
added in series with the NVM cells
to prevent cross talk or interference
between cells in the cross-point
array, which is referred to as oneselector and one-resistor (1S1R)
architecture. The cross-point array
can support PCRAM and RRAM but
generally does not support STTMRAM because of a very small on/
off ratio (~2×); thus, the sense margin becomes indistinguishable due
to the sneak path current.
The write/read schemes of the
cross-point array are as follows. To

S P R I N G 2 0 16

successfully program the NVM cells,
two common write schemes (V/2
and V/3) can be applied. Figure 3(a)
shows the voltage bias conditions
for the V/2 scheme. In the V/2
scheme, for the set operation, the
selected cell's WL and BL are biased
at the write voltage Vw and ground,
respectively. For the reset operation, the bias conditions on WL
and BL are reversed for the bipolar switching. In both set and reset
operations, all the unselected WLs
and BLs are biased at Vw /2. Therefore, only the selected cell sees a
full Vw , while the half-selected cells
along the selected WL or BL see a
half Vw and all the other unselected
cells in the array see zero voltage
[in reality, due to the current-resistance (IR) drop along the interconnect, the voltage is not perfectly

IEEE SOLID-STATE CIRCUITS MAGAZINE

zero though]. Here the assumption
is that Vw /2 should not disturb the
half-selected cell's resistance. Figure 3(b) shows the voltage bias conditions for the V/3 scheme. In the
V/3 scheme, for the set operation,
the selected cell's WL and BL are
biased at the write voltage Vw and
ground, respectively. For the reset
operation, the bias conditions on
WL and BL are reversed for the bipolar switching. The unselected WLs
and BLs are biased at 1/3 Vw and
2/3 Vw for the set operation, respectively. The unselected WLs and BLs
are biased at 2/3 Vw and 1/3 Vw for
the reset operation, respectively. In
this way, the selected cell sees Vw,
while all other unselected cells in
the array only see 1/3 Vw . Here the
assumption relaxes so that 1/3 Vw
should not disturb the unselected
cell's resistance. The pros and cons
of these two write schemes can
be summarized as follows: the V/2
scheme typically has less power
consumption than the V/3 scheme.
This is because the unselected cells
(not along the selected WL and BL)
in the V/2 scheme see zero voltage
ideally, while all the unselected cells
in the V/3 scheme see 1/3 Vw , thus
consuming static power during the
write period. On the other hand, the
V/3 scheme has better immunity to
the write disturbance than the V/2
scheme, as the maximum voltage
that the unselected cells see is 1/3
Vw in the V/3 scheme while is 1/2
Vw in the V/2 scheme. It is possible
to have multiple-bit parallel write in
the cross-point array with either the
V/2 or V/3 scheme by biasing multiple BLs (or WLs) to be ground in
the set (or reset) operation. The penalty for multiple-bit parallel write is
a larger driver size at each row (or
column) as it has to deliver the multiple write current in addition to the
sneak path via the unselected cells.
Figure 3(c) shows the read scheme
for the cross-point array. All the columns are biased at the read voltage
Vr , while the selected row is biased
at ground and the unselected rows
are biased at Vr . Therefore, only the

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016